diff --git a/.gitignore b/.gitignore index 1d74e219..78e639e0 100644 --- a/.gitignore +++ b/.gitignore @@ -1 +1,16 @@ .vscode/ + +# folders (and all of their contents) that should always be ignored, +# anywhere in the repo +.Xil/ + +# file patterns that should always be ignored (journal files, log +# files, dump files that are created upon Vivado/SDK errors) +*.jou +*.log +*.backup.jou +*.backup.log +*.upgrade_log +*.dmp +vivado_pid* +*~ diff --git a/adi_library/axi_ad5766/axi_ad5766_ip.log b/adi_library/axi_ad5766/axi_ad5766_ip.log deleted file mode 100644 index 9caf8787..00000000 --- a/adi_library/axi_ad5766/axi_ad5766_ip.log +++ /dev/null @@ -1,1490 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad5766_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad5766 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad5766 [list \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/util_pulse_gen.v" \ -# "up_ad5766_sequencer.v" \ -# "axi_ad5766.v" ] -# adi_ip_properties axi_ad5766 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_wr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dma'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_10' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_11' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_12' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_13' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_14' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_15' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_4' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_5' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_6' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_7' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_8' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_9' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_wr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port SDO_READY on bus interface abstraction spi_engine_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port SDO_VALID on bus interface abstraction spi_engine_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port SDI_READY on bus interface abstraction spi_engine_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port SDI_VALID on bus interface abstraction spi_engine_ctrl_rtl for interface type master. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'spi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 'spi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'spi_resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_xfer_req' and definition port 'XFER_REQ'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_ready' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data_valid' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_12': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_13': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_14': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_15': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_12': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_13': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_14': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_15': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_ready' and definition port 'SYNC_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_valid' and definition port 'SYNC_VALID'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_data' and definition port 'SYNC_DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_ready' and definition port 'CMD_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_valid' and definition port 'CMD_VALID'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'CMD_DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'SDO_DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data' and definition port 'SDI_DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_ready' and definition port 'SYNC_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_valid' and definition port 'SYNC_VALID'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_data' and definition port 'SYNC_DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDO_READY" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDO_VALID" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDI_READY" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDI_VALID" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ctrl_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dma_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'spi_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad5766 "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# } -# adi_add_bus "spi_engine_ctrl" "master" \ -# "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_ctrl:1.0" \ -# { -# {"cmd_ready" "CMD_READY"} \ -# {"cmd_valid" "CMD_VALID"} \ -# {"cmd_data" "CMD_DATA"} \ -# {"sdo_data_ready" "SDO_READY"} \ -# {"sdo_data_valid" "SDO_VALID"} \ -# {"sdo_data" "SDO_DATA"} \ -# {"sdi_data_ready" "SDI_READY"} \ -# {"sdi_data_valid" "SDI_VALID"} \ -# {"sdi_data" "SDI_DATA"} \ -# {"sync_ready" "SYNC_READY"} \ -# {"sync_valid" "SYNC_VALID"} \ -# {"sync_data" "SYNC_DATA"} \ -# } -# adi_add_bus "spi_engine_offload_ctrl" "slave" \ -# "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_offload_ctrl:1.0" \ -# { \ -# { "ctrl_cmd_wr_en" "CMD_WR_EN"} \ -# { "ctrl_cmd_wr_data" "CMD_WR_DATA"} \ -# { "ctrl_enable" "ENABLE"} \ -# { "ctrl_enabled" "ENABLED"} \ -# { "ctrl_mem_reset" "MEM_RESET"} \ -# } -# adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl" -# adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" -# adi_add_bus_clock "dma_clk" "dma_fifo_tx" -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:07:25 2021... diff --git a/adi_library/axi_ad5766/vivado.jou b/adi_library/axi_ad5766/vivado.jou deleted file mode 100644 index 8f253ef1..00000000 --- a/adi_library/axi_ad5766/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:07:12 2021 -# Process ID: 3020 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766 -# Command line: vivado -mode batch -source axi_ad5766_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766/vivado.jou -#----------------------------------------------------------- -source axi_ad5766_ip.tcl diff --git a/adi_library/axi_ad5766/vivado.log b/adi_library/axi_ad5766/vivado.log deleted file mode 100644 index f83732e9..00000000 --- a/adi_library/axi_ad5766/vivado.log +++ /dev/null @@ -1,1495 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:07:12 2021 -# Process ID: 3020 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766 -# Command line: vivado -mode batch -source axi_ad5766_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766/vivado.jou -#----------------------------------------------------------- -source axi_ad5766_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad5766 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad5766 [list \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/util_pulse_gen.v" \ -# "up_ad5766_sequencer.v" \ -# "axi_ad5766.v" ] -# adi_ip_properties axi_ad5766 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_wr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dma'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_10' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_11' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_12' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_13' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_14' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_15' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_4' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_5' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_6' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_7' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_8' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_9' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_wr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port SDO_READY on bus interface abstraction spi_engine_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port SDO_VALID on bus interface abstraction spi_engine_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port SDI_READY on bus interface abstraction spi_engine_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port SDI_VALID on bus interface abstraction spi_engine_ctrl_rtl for interface type master. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'spi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 'spi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'spi_resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_xfer_req' and definition port 'XFER_REQ'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_ready' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data_valid' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_12': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_13': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_14': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_15': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_12': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_13': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_14': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_15': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_ready' and definition port 'SYNC_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_valid' and definition port 'SYNC_VALID'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_data' and definition port 'SYNC_DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_ready' and definition port 'CMD_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_valid' and definition port 'CMD_VALID'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'CMD_DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'SDO_DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data' and definition port 'SDI_DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_ready' and definition port 'SYNC_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_valid' and definition port 'SYNC_VALID'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_data' and definition port 'SYNC_DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDO_READY" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDO_VALID" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDI_READY" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDI_VALID" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ctrl_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dma_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'spi_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad5766 "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# } -# adi_add_bus "spi_engine_ctrl" "master" \ -# "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_ctrl:1.0" \ -# { -# {"cmd_ready" "CMD_READY"} \ -# {"cmd_valid" "CMD_VALID"} \ -# {"cmd_data" "CMD_DATA"} \ -# {"sdo_data_ready" "SDO_READY"} \ -# {"sdo_data_valid" "SDO_VALID"} \ -# {"sdo_data" "SDO_DATA"} \ -# {"sdi_data_ready" "SDI_READY"} \ -# {"sdi_data_valid" "SDI_VALID"} \ -# {"sdi_data" "SDI_DATA"} \ -# {"sync_ready" "SYNC_READY"} \ -# {"sync_valid" "SYNC_VALID"} \ -# {"sync_data" "SYNC_DATA"} \ -# } -# adi_add_bus "spi_engine_offload_ctrl" "slave" \ -# "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_offload_ctrl:1.0" \ -# { \ -# { "ctrl_cmd_wr_en" "CMD_WR_EN"} \ -# { "ctrl_cmd_wr_data" "CMD_WR_DATA"} \ -# { "ctrl_enable" "ENABLE"} \ -# { "ctrl_enabled" "ENABLED"} \ -# { "ctrl_mem_reset" "MEM_RESET"} \ -# } -# adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl" -# adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" -# adi_add_bus_clock "dma_clk" "dma_fifo_tx" -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:07:25 2021... diff --git a/adi_library/axi_ad6676/axi_ad6676_ip.log b/adi_library/axi_ad6676/axi_ad6676_ip.log deleted file mode 100644 index 31f0c53b..00000000 --- a/adi_library/axi_ad6676/axi_ad6676_ip.log +++ /dev/null @@ -1,1334 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad6676_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad6676 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad6676'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad6676 [list \ -# "axi_ad6676.v" ] -# adi_ip_properties axi_ad6676 -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad6676 "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \ -# } -# set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:07:33 2021... diff --git a/adi_library/axi_ad6676/vivado.jou b/adi_library/axi_ad6676/vivado.jou deleted file mode 100644 index 21bc847f..00000000 --- a/adi_library/axi_ad6676/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:07:25 2021 -# Process ID: 3124 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad6676 -# Command line: vivado -mode batch -source axi_ad6676_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad6676/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad6676/vivado.jou -#----------------------------------------------------------- -source axi_ad6676_ip.tcl diff --git a/adi_library/axi_ad6676/vivado.log b/adi_library/axi_ad6676/vivado.log deleted file mode 100644 index 6c259b9d..00000000 --- a/adi_library/axi_ad6676/vivado.log +++ /dev/null @@ -1,1339 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:07:25 2021 -# Process ID: 3124 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad6676 -# Command line: vivado -mode batch -source axi_ad6676_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad6676/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad6676/vivado.jou -#----------------------------------------------------------- -source axi_ad6676_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad6676 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad6676'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad6676 [list \ -# "axi_ad6676.v" ] -# adi_ip_properties axi_ad6676 -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad6676 "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \ -# } -# set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:07:33 2021... diff --git a/adi_library/axi_ad7616/axi_ad7616_ip.log b/adi_library/axi_ad7616/axi_ad7616_ip.log deleted file mode 100644 index 19c3681e..00000000 --- a/adi_library/axi_ad7616/axi_ad7616_ip.log +++ /dev/null @@ -1,1090 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad7616_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad7616 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad7616 [list \ -# "$ad_hdl_dir/library/common/ad_edge_detect.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "axi_ad7616_control.v" \ -# "axi_ad7616_pif.v" \ -# "axi_ad7616_maxis2wrfifo.v" \ -# "axi_ad7616.v" ] -# adi_ip_properties axi_ad7616 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_edge_detect.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_edge_detect.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_10' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_11' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_12' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_13' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_14' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_15' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_4' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_5' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_6' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_7' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_8' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_9' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_n' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port CS on bus interface abstraction spi_master_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_rd_n' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_n': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_n': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_sclk' and definition port 'SCLK'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_sdi' and definition port 'SDI'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_sdo' and definition port 'SDO'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "CS" of the bus abstraction "analog.com:interface:spi_master_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_add_core_dependencies { \ -# analog.com:user:spi_engine_execution:1.0 \ -# analog.com:user:axi_spi_engine:1.0 \ -# analog.com:user:spi_engine_offload:1.0 \ -# analog.com:user:spi_engine_interconnect:1.0 \ -# } -# set_property DRIVER_VALUE "0" [ipx::get_ports rx_db_i] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:08:15 2021... diff --git a/adi_library/axi_ad7616/vivado.jou b/adi_library/axi_ad7616/vivado.jou deleted file mode 100644 index 041c0b7a..00000000 --- a/adi_library/axi_ad7616/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:08:05 2021 -# Process ID: 3419 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616 -# Command line: vivado -mode batch -source axi_ad7616_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616/vivado.jou -#----------------------------------------------------------- -source axi_ad7616_ip.tcl diff --git a/adi_library/axi_ad7616/vivado.log b/adi_library/axi_ad7616/vivado.log deleted file mode 100644 index 51edb642..00000000 --- a/adi_library/axi_ad7616/vivado.log +++ /dev/null @@ -1,1095 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:08:05 2021 -# Process ID: 3419 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616 -# Command line: vivado -mode batch -source axi_ad7616_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616/vivado.jou -#----------------------------------------------------------- -source axi_ad7616_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad7616 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad7616 [list \ -# "$ad_hdl_dir/library/common/ad_edge_detect.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "axi_ad7616_control.v" \ -# "axi_ad7616_pif.v" \ -# "axi_ad7616_maxis2wrfifo.v" \ -# "axi_ad7616.v" ] -# adi_ip_properties axi_ad7616 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_edge_detect.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_edge_detect.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_10' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_11' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_12' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_13' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_14' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_15' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_4' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_5' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_6' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_7' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_8' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_9' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_n' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port CS on bus interface abstraction spi_master_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_rd_n' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_n': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_n': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_sclk' and definition port 'SCLK'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_sdi' and definition port 'SDI'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_sdo' and definition port 'SDO'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "CS" of the bus abstraction "analog.com:interface:spi_master_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_add_core_dependencies { \ -# analog.com:user:spi_engine_execution:1.0 \ -# analog.com:user:axi_spi_engine:1.0 \ -# analog.com:user:spi_engine_offload:1.0 \ -# analog.com:user:spi_engine_interconnect:1.0 \ -# } -# set_property DRIVER_VALUE "0" [ipx::get_ports rx_db_i] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:08:15 2021... diff --git a/adi_library/axi_ad9122/axi_ad9122_ip.log b/adi_library/axi_ad9122/axi_ad9122_ip.log deleted file mode 100644 index 95ed0d79..00000000 --- a/adi_library/axi_ad9122/axi_ad9122_ip.log +++ /dev/null @@ -1,1257 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9122_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9122 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9122 [list \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9122_channel.v" \ -# "axi_ad9122_core.v" \ -# "axi_ad9122_if.v" \ -# "axi_ad9122_constr.xdc" \ -# "axi_ad9122.v" ] -# adi_ip_properties axi_ad9122 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_in' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_div_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-533] HDL Parameter 'MMCM_CLKIN_PERIOD (Mmcm Clkin Period)': Missing data type -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_sync_out' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_div_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_div_clk': FREQ_HZ bus parameter is missing for output clock interface. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9122 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface dac_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk_in_p' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk_in_n' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_clk_out_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk_out_p' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_clk_out_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk_out_n' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_div_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_div_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:08:35 2021... diff --git a/adi_library/axi_ad9122/vivado.jou b/adi_library/axi_ad9122/vivado.jou deleted file mode 100644 index 10376f07..00000000 --- a/adi_library/axi_ad9122/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:08:15 2021 -# Process ID: 3483 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122 -# Command line: vivado -mode batch -source axi_ad9122_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122/vivado.jou -#----------------------------------------------------------- -source axi_ad9122_ip.tcl diff --git a/adi_library/axi_ad9122/vivado.log b/adi_library/axi_ad9122/vivado.log deleted file mode 100644 index 906d8329..00000000 --- a/adi_library/axi_ad9122/vivado.log +++ /dev/null @@ -1,1262 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:08:15 2021 -# Process ID: 3483 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122 -# Command line: vivado -mode batch -source axi_ad9122_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122/vivado.jou -#----------------------------------------------------------- -source axi_ad9122_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9122 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9122 [list \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9122_channel.v" \ -# "axi_ad9122_core.v" \ -# "axi_ad9122_if.v" \ -# "axi_ad9122_constr.xdc" \ -# "axi_ad9122.v" ] -# adi_ip_properties axi_ad9122 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9122'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_in' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_n_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_p_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_div_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-533] HDL Parameter 'MMCM_CLKIN_PERIOD (Mmcm Clkin Period)': Missing data type -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_sync_out' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_n_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_p_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_div_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_div_clk': FREQ_HZ bus parameter is missing for output clock interface. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9122 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface dac_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk_in_p' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk_in_n' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_clk_out_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk_out_p' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_clk_out_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk_out_n' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_div_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_div_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:08:35 2021... diff --git a/adi_library/axi_ad9144/axi_ad9144_ip.log b/adi_library/axi_ad9144/axi_ad9144_ip.log deleted file mode 100644 index 7ee80358..00000000 --- a/adi_library/axi_ad9144/axi_ad9144_ip.log +++ /dev/null @@ -1,1035 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9144_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9144 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9144'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9144 [list \ -# "axi_ad9144.v" ] -# adi_ip_properties axi_ad9144 -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dac_valid_s' has a dependency on the module local parameter or undefined parameter 'NUM_CHANNELS'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dac_enable_s' has a dependency on the module local parameter or undefined parameter 'NUM_CHANNELS'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dac_ddata_s' has a dependency on the module local parameter or undefined parameter 'NUM_CHANNELS'. -WARNING: [IP_Flow 19-5150] The Range '((128 * QUAD_OR_DUAL_N) + 127):0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_2' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_3' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((128 * QUAD_OR_DUAL_N) + 127):0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'tx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9144 "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \ -# } -# adi_set_ports_dependency "dac_valid_2" "QUAD_OR_DUAL_N == 1" -# adi_set_ports_dependency "dac_valid_3" "QUAD_OR_DUAL_N == 1" -# adi_set_ports_dependency "dac_enable_2" "QUAD_OR_DUAL_N == 1" -# adi_set_ports_dependency "dac_enable_3" "QUAD_OR_DUAL_N == 1" -# adi_set_ports_dependency "dac_ddata_2" "QUAD_OR_DUAL_N == 1" "0" -# adi_set_ports_dependency "dac_ddata_3" "QUAD_OR_DUAL_N == 1" "0" -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:09:04 2021... diff --git a/adi_library/axi_ad9144/vivado.jou b/adi_library/axi_ad9144/vivado.jou deleted file mode 100644 index 37ddb96f..00000000 --- a/adi_library/axi_ad9144/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:08:57 2021 -# Process ID: 3706 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9144 -# Command line: vivado -mode batch -source axi_ad9144_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9144/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9144/vivado.jou -#----------------------------------------------------------- -source axi_ad9144_ip.tcl diff --git a/adi_library/axi_ad9144/vivado.log b/adi_library/axi_ad9144/vivado.log deleted file mode 100644 index 8b5e9077..00000000 --- a/adi_library/axi_ad9144/vivado.log +++ /dev/null @@ -1,1040 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:08:57 2021 -# Process ID: 3706 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9144 -# Command line: vivado -mode batch -source axi_ad9144_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9144/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9144/vivado.jou -#----------------------------------------------------------- -source axi_ad9144_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9144 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9144'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9144 [list \ -# "axi_ad9144.v" ] -# adi_ip_properties axi_ad9144 -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dac_valid_s' has a dependency on the module local parameter or undefined parameter 'NUM_CHANNELS'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dac_enable_s' has a dependency on the module local parameter or undefined parameter 'NUM_CHANNELS'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dac_ddata_s' has a dependency on the module local parameter or undefined parameter 'NUM_CHANNELS'. -WARNING: [IP_Flow 19-5150] The Range '((128 * QUAD_OR_DUAL_N) + 127):0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_2' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_3' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((128 * QUAD_OR_DUAL_N) + 127):0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'tx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9144 "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \ -# } -# adi_set_ports_dependency "dac_valid_2" "QUAD_OR_DUAL_N == 1" -# adi_set_ports_dependency "dac_valid_3" "QUAD_OR_DUAL_N == 1" -# adi_set_ports_dependency "dac_enable_2" "QUAD_OR_DUAL_N == 1" -# adi_set_ports_dependency "dac_enable_3" "QUAD_OR_DUAL_N == 1" -# adi_set_ports_dependency "dac_ddata_2" "QUAD_OR_DUAL_N == 1" "0" -# adi_set_ports_dependency "dac_ddata_3" "QUAD_OR_DUAL_N == 1" "0" -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:09:04 2021... diff --git a/adi_library/axi_ad9152/axi_ad9152_ip.log b/adi_library/axi_ad9152/axi_ad9152_ip.log deleted file mode 100644 index e9051846..00000000 --- a/adi_library/axi_ad9152/axi_ad9152_ip.log +++ /dev/null @@ -1,1499 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9152_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9152 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9152'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9152 [list \ -# "axi_ad9152.v" ] -# adi_ip_properties axi_ad9152 -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_100' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_101' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_102' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_103' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_104' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_105' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_106' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_107' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_108' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_109' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_110' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_111' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_112' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_113' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_114' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_115' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_116' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_117' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_118' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_119' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_120' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_121' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_122' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_123' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_124' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_125' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_126' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_127' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_64' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_65' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_66' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_67' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_68' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_69' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_70' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_71' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_72' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_73' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'tx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9152 "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \ -# } -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:09:12 2021... diff --git a/adi_library/axi_ad9152/vivado.jou b/adi_library/axi_ad9152/vivado.jou deleted file mode 100644 index bca7b357..00000000 --- a/adi_library/axi_ad9152/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:09:05 2021 -# Process ID: 3772 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9152 -# Command line: vivado -mode batch -source axi_ad9152_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9152/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9152/vivado.jou -#----------------------------------------------------------- -source axi_ad9152_ip.tcl diff --git a/adi_library/axi_ad9152/vivado.log b/adi_library/axi_ad9152/vivado.log deleted file mode 100644 index 6241b303..00000000 --- a/adi_library/axi_ad9152/vivado.log +++ /dev/null @@ -1,1504 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:09:05 2021 -# Process ID: 3772 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9152 -# Command line: vivado -mode batch -source axi_ad9152_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9152/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9152/vivado.jou -#----------------------------------------------------------- -source axi_ad9152_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9152 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9152'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9152 [list \ -# "axi_ad9152.v" ] -# adi_ip_properties axi_ad9152 -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_100' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_101' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_102' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_103' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_104' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_105' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_106' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_107' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_108' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_109' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_110' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_111' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_112' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_113' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_114' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_115' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_116' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_117' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_118' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_119' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_120' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_121' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_122' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_123' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_124' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_125' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_126' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_127' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_64' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_65' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_66' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_67' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_68' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_69' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_70' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_71' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_72' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_73' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'tx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9152 "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \ -# } -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:09:12 2021... diff --git a/adi_library/axi_ad9162/axi_ad9162_ip.log b/adi_library/axi_ad9162/axi_ad9162_ip.log deleted file mode 100644 index 89ebd806..00000000 --- a/adi_library/axi_ad9162/axi_ad9162_ip.log +++ /dev/null @@ -1,1798 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9162_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9162 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9162 [list \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "axi_ad9162_channel.v" \ -# "axi_ad9162_core.v" \ -# "axi_ad9162_if.v" \ -# "axi_ad9162.v" ] -# adi_ip_properties axi_ad9162 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_100' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_101' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_102' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_103' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_104' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_105' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_106' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_107' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_108' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_109' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_110' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_111' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_112' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_113' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_114' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_115' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_116' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_117' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_118' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_119' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_120' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_121' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_122' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_123' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_124' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_125' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_126' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_127' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_128' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_129' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_130' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_131' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_132' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_133' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_134' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_135' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_136' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_137' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_138' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_139' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_140' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_141' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_142' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_143' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_144' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_145' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_146' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_147' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_148' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_149' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_150' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_151' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_152' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_153' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_154' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_155' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_156' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_157' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_158' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_159' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_160' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_161' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_162' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_163' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_164' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_165' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_166' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_167' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_168' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_169' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_170' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_171' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_172' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_173' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_174' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_175' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_176' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_177' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_178' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_179' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_180' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_181' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_182' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_183' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_184' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_185' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_186' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_187' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_188' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_128': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_129': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_130': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_131': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_132': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_133': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_134': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_135': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_136': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_137': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_138': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_139': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_140': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_141': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_142': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_143': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_144': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_145': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_146': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_147': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_148': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_149': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_150': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_151': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_152': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_153': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_154': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_155': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_156': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_157': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_158': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_159': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_160': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_161': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_162': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_163': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_164': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_165': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_166': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_167': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_168': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_169': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_170': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_171': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_172': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_173': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_174': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_175': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_176': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_177': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_178': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_179': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_180': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_181': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_182': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_183': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_184': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_185': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_186': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_187': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_188': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_189': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_190': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_191': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_192': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_193': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_194': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_195': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_196': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_197': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_198': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_199': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_200': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_201': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_202': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_203': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_204': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_205': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_206': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_207': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_208': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_209': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_210': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_211': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_212': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_213': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_214': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_215': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_216': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_217': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_218': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_219': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_220': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_221': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_222': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_223': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_224': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_225': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_226': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_227': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_228': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_229': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_230': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_231': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_232': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_233': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_234': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_235': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_236': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_237': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_238': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_239': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_240': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_241': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_242': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_243': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_244': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_245': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_246': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_247': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_248': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_249': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_250': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_251': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_252': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_253': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_254': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_255': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'tx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9162 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:09:30 2021... diff --git a/adi_library/axi_ad9162/vivado.jou b/adi_library/axi_ad9162/vivado.jou deleted file mode 100644 index 68e3d314..00000000 --- a/adi_library/axi_ad9162/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:09:13 2021 -# Process ID: 3828 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162 -# Command line: vivado -mode batch -source axi_ad9162_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162/vivado.jou -#----------------------------------------------------------- -source axi_ad9162_ip.tcl diff --git a/adi_library/axi_ad9162/vivado.log b/adi_library/axi_ad9162/vivado.log deleted file mode 100644 index ca836948..00000000 --- a/adi_library/axi_ad9162/vivado.log +++ /dev/null @@ -1,1803 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:09:13 2021 -# Process ID: 3828 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162 -# Command line: vivado -mode batch -source axi_ad9162_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162/vivado.jou -#----------------------------------------------------------- -source axi_ad9162_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9162 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9162 [list \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "axi_ad9162_channel.v" \ -# "axi_ad9162_core.v" \ -# "axi_ad9162_if.v" \ -# "axi_ad9162.v" ] -# adi_ip_properties axi_ad9162 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_100' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_101' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_102' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_103' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_104' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_105' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_106' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_107' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_108' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_109' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_110' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_111' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_112' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_113' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_114' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_115' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_116' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_117' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_118' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_119' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_120' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_121' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_122' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_123' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_124' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_125' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_126' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_127' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_128' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_129' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_130' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_131' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_132' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_133' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_134' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_135' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_136' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_137' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_138' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_139' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_140' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_141' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_142' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_143' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_144' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_145' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_146' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_147' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_148' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_149' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_150' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_151' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_152' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_153' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_154' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_155' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_156' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_157' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_158' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_159' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_160' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_161' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_162' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_163' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_164' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_165' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_166' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_167' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_168' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_169' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_170' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_171' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_172' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_173' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_174' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_175' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_176' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_177' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_178' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_179' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_180' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_181' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_182' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_183' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_184' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_185' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_186' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_187' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_188' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_128': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_129': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_130': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_131': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_132': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_133': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_134': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_135': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_136': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_137': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_138': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_139': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_140': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_141': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_142': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_143': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_144': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_145': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_146': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_147': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_148': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_149': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_150': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_151': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_152': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_153': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_154': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_155': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_156': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_157': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_158': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_159': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_160': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_161': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_162': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_163': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_164': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_165': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_166': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_167': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_168': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_169': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_170': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_171': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_172': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_173': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_174': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_175': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_176': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_177': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_178': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_179': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_180': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_181': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_182': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_183': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_184': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_185': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_186': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_187': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_188': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_189': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_190': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_191': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_192': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_193': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_194': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_195': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_196': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_197': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_198': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_199': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_200': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_201': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_202': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_203': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_204': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_205': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_206': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_207': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_208': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_209': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_210': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_211': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_212': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_213': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_214': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_215': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_216': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_217': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_218': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_219': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_220': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_221': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_222': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_223': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_224': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_225': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_226': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_227': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_228': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_229': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_230': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_231': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_232': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_233': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_234': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_235': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_236': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_237': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_238': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_239': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_240': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_241': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_242': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_243': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_244': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_245': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_246': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_247': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_248': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_249': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_250': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_251': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_252': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_253': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_254': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_255': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'tx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9162 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:09:30 2021... diff --git a/adi_library/axi_ad9250/axi_ad9250_ip.log b/adi_library/axi_ad9250/axi_ad9250_ip.log deleted file mode 100644 index 7faabdec..00000000 --- a/adi_library/axi_ad9250/axi_ad9250_ip.log +++ /dev/null @@ -1,1403 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9250_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9250 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9250'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9250 [list \ -# "axi_ad9250.v" ] -# adi_ip_properties axi_ad9250 -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9250 "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \ -# } -# set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:09:38 2021... diff --git a/adi_library/axi_ad9250/vivado.jou b/adi_library/axi_ad9250/vivado.jou deleted file mode 100644 index 4abad552..00000000 --- a/adi_library/axi_ad9250/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:09:30 2021 -# Process ID: 3926 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9250 -# Command line: vivado -mode batch -source axi_ad9250_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9250/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9250/vivado.jou -#----------------------------------------------------------- -source axi_ad9250_ip.tcl diff --git a/adi_library/axi_ad9250/vivado.log b/adi_library/axi_ad9250/vivado.log deleted file mode 100644 index e05e17bf..00000000 --- a/adi_library/axi_ad9250/vivado.log +++ /dev/null @@ -1,1408 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:09:30 2021 -# Process ID: 3926 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9250 -# Command line: vivado -mode batch -source axi_ad9250_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9250/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9250/vivado.jou -#----------------------------------------------------------- -source axi_ad9250_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9250 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9250'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9250 [list \ -# "axi_ad9250.v" ] -# adi_ip_properties axi_ad9250 -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9250 "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \ -# } -# set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:09:38 2021... diff --git a/adi_library/axi_ad9265/axi_ad9265_ip.log b/adi_library/axi_ad9265/axi_ad9265_ip.log deleted file mode 100644 index ecb0b9f2..00000000 --- a/adi_library/axi_ad9265/axi_ad9265_ip.log +++ /dev/null @@ -1,1201 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9265_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9265 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9265 [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9265_pnmon.v" \ -# "axi_ad9265_if.v" \ -# "axi_ad9265_channel.v" \ -# "axi_ad9265.v" ] -# adi_ip_properties axi_ad9265 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9265 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk_in_P xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_in_P' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_in_n' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:09:55 2021... diff --git a/adi_library/axi_ad9265/vivado.jou b/adi_library/axi_ad9265/vivado.jou deleted file mode 100644 index f22fa698..00000000 --- a/adi_library/axi_ad9265/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:09:38 2021 -# Process ID: 3982 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265 -# Command line: vivado -mode batch -source axi_ad9265_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265/vivado.jou -#----------------------------------------------------------- -source axi_ad9265_ip.tcl diff --git a/adi_library/axi_ad9265/vivado.log b/adi_library/axi_ad9265/vivado.log deleted file mode 100644 index 1f8791b9..00000000 --- a/adi_library/axi_ad9265/vivado.log +++ /dev/null @@ -1,1206 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:09:38 2021 -# Process ID: 3982 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265 -# Command line: vivado -mode batch -source axi_ad9265_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265/vivado.jou -#----------------------------------------------------------- -source axi_ad9265_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9265 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9265 [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9265_pnmon.v" \ -# "axi_ad9265_if.v" \ -# "axi_ad9265_channel.v" \ -# "axi_ad9265.v" ] -# adi_ip_properties axi_ad9265 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9265'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9265 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk_in_P xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_in_P' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_in_n' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:09:55 2021... diff --git a/adi_library/axi_ad9361/axi_ad9361_ip.log b/adi_library/axi_ad9361/axi_ad9361_ip.log deleted file mode 100644 index 902366a9..00000000 --- a/adi_library/axi_ad9361/axi_ad9361_ip.log +++ /dev/null @@ -1,1556 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9361_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9361 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9361 [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_out.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_iqcor.v" \ -# "$ad_hdl_dir/library/common/ad_addsub.v" \ -# "$ad_hdl_dir/library/common/ad_tdd_control.v" \ -# "$ad_hdl_dir/library/common/ad_pps_receiver.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/common/ad_pps_receiver_constr.ttcl" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9361_constr.xdc" \ -# "xilinx/axi_ad9361_lvds_if.v" \ -# "xilinx/axi_ad9361_cmos_if.v" \ -# "axi_ad9361_rx_pnmon.v" \ -# "axi_ad9361_rx_channel.v" \ -# "axi_ad9361_rx.v" \ -# "axi_ad9361_tx_channel.v" \ -# "axi_ad9361_tx.v" \ -# "axi_ad9361_tdd.v" \ -# "axi_ad9361_tdd_if.v" \ -# "axi_ad9361.v" ] -# adi_ip_properties axi_ad9361 -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pps_receiver_constr.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_addsub.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pps_receiver.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_tdd_control.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_tdd_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_addsub.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pps_receiver.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_tdd_control.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_tdd_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'rx_in'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx_out'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_in' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'rx_in'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx_out'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'gps_pps_irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_sync_out' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tdd_sync_cntr' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd_cntr': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd_cntr': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "SYNC_READY" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "SYNC_VALID" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'l_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'l_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_ttcl axi_ad9361 "../common/ad_pps_receiver_constr.ttcl" -# adi_init_bd_tcl -# adi_ip_bd axi_ad9361 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *rx_clk_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *rx_frame_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *rx_data_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *gpio_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *gps_pps* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 0} \ -# [ipx::get_ports rx_clk_in_p -of_objects [ipx::current_core]] \ -# [ipx::get_ports rx_clk_in_n -of_objects [ipx::current_core]] \ -# [ipx::get_ports rx_frame_in_p -of_objects [ipx::current_core]] \ -# [ipx::get_ports rx_frame_in_n -of_objects [ipx::current_core]] \ -# [ipx::get_ports rx_data_in_p -of_objects [ipx::current_core]] \ -# [ipx::get_ports rx_data_in_n -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_clk_out_p -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_clk_out_n -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_frame_out_p -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_frame_out_n -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_data_out_p -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_data_out_n -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 1} \ -# [ipx::get_ports rx_clk_in -of_objects [ipx::current_core]] \ -# [ipx::get_ports rx_frame_in -of_objects [ipx::current_core]] \ -# [ipx::get_ports rx_data_in -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_clk_out -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_frame_out -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_data_out -of_objects [ipx::current_core]] -# ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ -# -of_objects [ipx::current_core]] -# set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ -# -of_objects [ipx::get_bus_interfaces s_axi_aclk \ -# -of_objects [ipx::current_core]]] -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface l_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'l_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rst'. -# set reset_intf [ipx::infer_bus_interface rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]] -# set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf] -# set_property value "ACTIVE_HIGH" $reset_polarity -# ipx::infer_bus_interface gps_pps_irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'gps_pps_irq' of definition 'xilinx.com:signal:interrupt:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'gps_pps_irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -# ipgui::remove_param -component [ipx::current_core] [ipgui::get_guiparamspec -name "RX_NODPA" -component [ipx::current_core]] -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:22:06 2021... diff --git a/adi_library/axi_ad9361/vivado.jou b/adi_library/axi_ad9361/vivado.jou deleted file mode 100644 index ab2f5bc3..00000000 --- a/adi_library/axi_ad9361/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:21:36 2021 -# Process ID: 66227 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361 -# Command line: vivado -mode batch -source axi_ad9361_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361/vivado.jou -#----------------------------------------------------------- -source axi_ad9361_ip.tcl diff --git a/adi_library/axi_ad9361/vivado.log b/adi_library/axi_ad9361/vivado.log deleted file mode 100644 index 3597b623..00000000 --- a/adi_library/axi_ad9361/vivado.log +++ /dev/null @@ -1,1561 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:21:36 2021 -# Process ID: 66227 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361 -# Command line: vivado -mode batch -source axi_ad9361_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361/vivado.jou -#----------------------------------------------------------- -source axi_ad9361_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9361 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9361 [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_out.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_iqcor.v" \ -# "$ad_hdl_dir/library/common/ad_addsub.v" \ -# "$ad_hdl_dir/library/common/ad_tdd_control.v" \ -# "$ad_hdl_dir/library/common/ad_pps_receiver.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/common/ad_pps_receiver_constr.ttcl" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9361_constr.xdc" \ -# "xilinx/axi_ad9361_lvds_if.v" \ -# "xilinx/axi_ad9361_cmos_if.v" \ -# "axi_ad9361_rx_pnmon.v" \ -# "axi_ad9361_rx_channel.v" \ -# "axi_ad9361_rx.v" \ -# "axi_ad9361_tx_channel.v" \ -# "axi_ad9361_tx.v" \ -# "axi_ad9361_tdd.v" \ -# "axi_ad9361_tdd_if.v" \ -# "axi_ad9361.v" ] -# adi_ip_properties axi_ad9361 -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pps_receiver_constr.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_addsub.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pps_receiver.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_tdd_control.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_tdd_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_addsub.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pps_receiver.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_tdd_control.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_tdd_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'rx_in'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx_out'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_in' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'rx_in'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx_out'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'gps_pps_irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_sync_out' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tdd_sync_cntr' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd_cntr': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd_cntr': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data_out_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "SYNC_READY" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "SYNC_VALID" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'l_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'l_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_ttcl axi_ad9361 "../common/ad_pps_receiver_constr.ttcl" -# adi_init_bd_tcl -# adi_ip_bd axi_ad9361 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *rx_clk_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *rx_frame_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *rx_data_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *gpio_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *gps_pps* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 0} \ -# [ipx::get_ports rx_clk_in_p -of_objects [ipx::current_core]] \ -# [ipx::get_ports rx_clk_in_n -of_objects [ipx::current_core]] \ -# [ipx::get_ports rx_frame_in_p -of_objects [ipx::current_core]] \ -# [ipx::get_ports rx_frame_in_n -of_objects [ipx::current_core]] \ -# [ipx::get_ports rx_data_in_p -of_objects [ipx::current_core]] \ -# [ipx::get_ports rx_data_in_n -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_clk_out_p -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_clk_out_n -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_frame_out_p -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_frame_out_n -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_data_out_p -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_data_out_n -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 1} \ -# [ipx::get_ports rx_clk_in -of_objects [ipx::current_core]] \ -# [ipx::get_ports rx_frame_in -of_objects [ipx::current_core]] \ -# [ipx::get_ports rx_data_in -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_clk_out -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_frame_out -of_objects [ipx::current_core]] \ -# [ipx::get_ports tx_data_out -of_objects [ipx::current_core]] -# ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ -# -of_objects [ipx::current_core]] -# set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ -# -of_objects [ipx::get_bus_interfaces s_axi_aclk \ -# -of_objects [ipx::current_core]]] -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface l_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'l_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rst'. -# set reset_intf [ipx::infer_bus_interface rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]] -# set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf] -# set_property value "ACTIVE_HIGH" $reset_polarity -# ipx::infer_bus_interface gps_pps_irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'gps_pps_irq' of definition 'xilinx.com:signal:interrupt:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'gps_pps_irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -# ipgui::remove_param -component [ipx::current_core] [ipgui::get_guiparamspec -name "RX_NODPA" -component [ipx::current_core]] -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:22:06 2021... diff --git a/adi_library/axi_ad9371/axi_ad9371_ip.log b/adi_library/axi_ad9371/axi_ad9371_ip.log deleted file mode 100644 index 95e73eb1..00000000 --- a/adi_library/axi_ad9371/axi_ad9371_ip.log +++ /dev/null @@ -1,2127 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9371_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9371 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9371 [list \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_iqcor.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ -# "axi_ad9371_if.v" \ -# "axi_ad9371_rx_channel.v" \ -# "axi_ad9371_rx.v" \ -# "axi_ad9371_rx_os.v" \ -# "axi_ad9371_tx_channel.v" \ -# "axi_ad9371_tx.v" \ -# "axi_ad9371.v" ] -# adi_ip_properties axi_ad9371 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx_os'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'dac_tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx_os'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'dac_tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_sync_out' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_os_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_os_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_os_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9371 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *adc_rx_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *adc_rx_os_valid* -of_objects [ipx::current_core]] -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:10:19 2021... diff --git a/adi_library/axi_ad9371/vivado.jou b/adi_library/axi_ad9371/vivado.jou deleted file mode 100644 index 0958dc06..00000000 --- a/adi_library/axi_ad9371/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:09:56 2021 -# Process ID: 4078 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371 -# Command line: vivado -mode batch -source axi_ad9371_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371/vivado.jou -#----------------------------------------------------------- -source axi_ad9371_ip.tcl diff --git a/adi_library/axi_ad9371/vivado.log b/adi_library/axi_ad9371/vivado.log deleted file mode 100644 index 77f66f3f..00000000 --- a/adi_library/axi_ad9371/vivado.log +++ /dev/null @@ -1,2132 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:09:56 2021 -# Process ID: 4078 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371 -# Command line: vivado -mode batch -source axi_ad9371_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371/vivado.jou -#----------------------------------------------------------- -source axi_ad9371_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9371 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9371 [list \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_iqcor.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ -# "axi_ad9371_if.v" \ -# "axi_ad9371_rx_channel.v" \ -# "axi_ad9371_rx.v" \ -# "axi_ad9371_rx_os.v" \ -# "axi_ad9371_tx_channel.v" \ -# "axi_ad9371_tx.v" \ -# "axi_ad9371.v" ] -# adi_ip_properties axi_ad9371 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9371'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx_os'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'dac_tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx_os'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'dac_tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_sync_out' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_os_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_os_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_os_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9371 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *adc_rx_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *adc_rx_os_valid* -of_objects [ipx::current_core]] -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:10:19 2021... diff --git a/adi_library/axi_ad9434/axi_ad9434_ip.log b/adi_library/axi_ad9434/axi_ad9434_ip.log deleted file mode 100644 index c842551a..00000000 --- a/adi_library/axi_ad9434/axi_ad9434_ip.log +++ /dev/null @@ -1,1409 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9434_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9434 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9434 [list \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9434_if.v" \ -# "axi_ad9434_pnmon.v" \ -# "axi_ad9434_core.v" \ -# "axi_ad9434_constr.xdc" \ -# "axi_ad9434.v" ] -# adi_ip_properties axi_ad9434 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9434 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:10:37 2021... diff --git a/adi_library/axi_ad9434/vivado.jou b/adi_library/axi_ad9434/vivado.jou deleted file mode 100644 index ed29777a..00000000 --- a/adi_library/axi_ad9434/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:10:20 2021 -# Process ID: 4188 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434 -# Command line: vivado -mode batch -source axi_ad9434_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434/vivado.jou -#----------------------------------------------------------- -source axi_ad9434_ip.tcl diff --git a/adi_library/axi_ad9434/vivado.log b/adi_library/axi_ad9434/vivado.log deleted file mode 100644 index 6aa1f43c..00000000 --- a/adi_library/axi_ad9434/vivado.log +++ /dev/null @@ -1,1414 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:10:20 2021 -# Process ID: 4188 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434 -# Command line: vivado -mode batch -source axi_ad9434_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434/vivado.jou -#----------------------------------------------------------- -source axi_ad9434_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9434 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9434 [list \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9434_if.v" \ -# "axi_ad9434_pnmon.v" \ -# "axi_ad9434_core.v" \ -# "axi_ad9434_constr.xdc" \ -# "axi_ad9434.v" ] -# adi_ip_properties axi_ad9434 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9434 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:10:37 2021... diff --git a/adi_library/axi_ad9467/axi_ad9467_ip.log b/adi_library/axi_ad9467/axi_ad9467_ip.log deleted file mode 100644 index 209abc96..00000000 --- a/adi_library/axi_ad9467/axi_ad9467_ip.log +++ /dev/null @@ -1,1193 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9467_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9467 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9467 [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9467_pnmon.v" \ -# "axi_ad9467_if.v" \ -# "axi_ad9467_channel.v" \ -# "axi_ad9467.v" ] -# adi_ip_properties axi_ad9467 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9467 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_in_p' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_in_n' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:10:54 2021... diff --git a/adi_library/axi_ad9467/vivado.jou b/adi_library/axi_ad9467/vivado.jou deleted file mode 100644 index 9c4c1634..00000000 --- a/adi_library/axi_ad9467/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:10:37 2021 -# Process ID: 4290 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467 -# Command line: vivado -mode batch -source axi_ad9467_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467/vivado.jou -#----------------------------------------------------------- -source axi_ad9467_ip.tcl diff --git a/adi_library/axi_ad9467/vivado.log b/adi_library/axi_ad9467/vivado.log deleted file mode 100644 index 6206484e..00000000 --- a/adi_library/axi_ad9467/vivado.log +++ /dev/null @@ -1,1198 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:10:37 2021 -# Process ID: 4290 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467 -# Command line: vivado -mode batch -source axi_ad9467_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467/vivado.jou -#----------------------------------------------------------- -source axi_ad9467_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9467 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9467 [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9467_pnmon.v" \ -# "axi_ad9467_if.v" \ -# "axi_ad9467_channel.v" \ -# "axi_ad9467.v" ] -# adi_ip_properties axi_ad9467 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9467'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9467 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_in_p' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_in_n' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:10:54 2021... diff --git a/adi_library/axi_ad9625/axi_ad9625_ip.log b/adi_library/axi_ad9625/axi_ad9625_ip.log deleted file mode 100644 index fb60bb6f..00000000 --- a/adi_library/axi_ad9625/axi_ad9625_ip.log +++ /dev/null @@ -1,2058 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9625_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9625 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9625 [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9625_pnmon.v" \ -# "axi_ad9625_channel.v" \ -# "axi_ad9625_if.v" \ -# "axi_ad9625.v" ] -# adi_ip_properties axi_ad9625 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_100' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_101' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_102' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_103' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_104' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_105' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_106' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_107' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_108' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_109' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_110' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_111' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_112' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_113' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_114' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_115' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_116' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_117' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_118' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_119' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_120' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_121' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_122' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_123' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_124' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_125' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_126' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_127' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_128' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_129' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_130' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_131' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_132' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_133' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_134' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_135' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_136' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_137' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_138' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_139' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_140' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_141' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_142' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_143' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_144' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_145' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_146' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_147' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_148' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_149' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_150' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_151' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_152' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_153' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_154' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_155' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_156' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_157' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_158' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_159' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_160' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_161' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_162' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_163' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_164' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_165' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_166' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_167' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_168' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_169' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_170' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_171' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_172' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_173' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_174' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_175' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_176' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_177' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_178' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_179' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_180' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_181' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_182' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_183' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_184' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_185' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_186' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_187' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_188' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_128': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_129': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_130': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_131': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_132': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_133': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_134': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_135': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_136': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_137': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_138': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_139': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_140': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_141': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_142': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_143': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_144': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_145': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_146': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_147': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_148': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_149': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_150': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_151': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_152': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_153': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_154': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_155': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_156': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_157': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_158': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_159': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_160': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_161': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_162': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_163': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_164': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_165': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_166': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_167': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_168': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_169': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_170': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_171': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_172': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_173': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_174': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_175': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_176': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_177': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_178': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_179': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_180': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_181': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_182': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_183': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_184': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_185': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_186': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_187': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_188': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_189': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_190': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_191': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_192': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_193': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_194': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_195': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_196': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_197': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_198': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_199': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_200': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_201': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_202': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_203': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_204': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_205': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_206': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_207': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_208': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_209': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_210': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_211': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_212': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_213': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_214': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_215': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_216': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_217': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_218': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_219': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_220': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_221': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_222': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_223': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_224': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_225': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_226': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_227': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_228': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_229': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_230': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_231': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_232': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_233': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_234': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_235': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_236': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_237': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_238': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_239': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_240': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_241': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_242': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_243': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_244': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_245': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_246': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_247': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_248': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_249': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_250': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_251': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_252': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_253': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_254': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_255': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_128': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_129': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_130': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_131': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_132': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_133': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_134': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_135': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_136': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_137': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_138': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_139': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_140': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_141': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_142': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_143': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_144': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_145': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_146': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_147': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_148': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_149': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_150': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_151': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_152': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_153': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_154': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_155': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_156': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_157': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_158': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_159': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_160': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_161': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_162': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_163': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_164': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_165': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_166': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_167': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_168': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_169': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_170': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_171': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_172': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_173': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_174': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_175': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_176': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_177': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_178': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_179': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_180': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_181': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_182': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_183': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_184': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_185': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_186': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_187': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_188': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_189': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_190': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_191': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_192': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_193': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_194': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_195': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_196': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_197': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_198': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_199': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_200': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_201': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_202': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_203': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_204': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_205': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_206': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_207': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_208': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_209': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_210': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_211': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_212': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_213': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_214': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_215': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_216': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_217': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_218': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_219': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_220': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_221': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_222': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_223': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_224': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_225': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_226': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_227': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_228': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_229': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_230': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_231': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_232': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_233': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_234': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_235': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_236': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_237': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_238': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_239': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_240': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_241': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_242': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_243': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_244': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_245': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_246': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_247': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_248': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_249': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_250': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_251': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_252': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_253': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_254': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_255': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9625 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:11:10 2021... diff --git a/adi_library/axi_ad9625/vivado.jou b/adi_library/axi_ad9625/vivado.jou deleted file mode 100644 index 31ef971c..00000000 --- a/adi_library/axi_ad9625/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:10:54 2021 -# Process ID: 4379 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625 -# Command line: vivado -mode batch -source axi_ad9625_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625/vivado.jou -#----------------------------------------------------------- -source axi_ad9625_ip.tcl diff --git a/adi_library/axi_ad9625/vivado.log b/adi_library/axi_ad9625/vivado.log deleted file mode 100644 index 5471ddff..00000000 --- a/adi_library/axi_ad9625/vivado.log +++ /dev/null @@ -1,2063 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:10:54 2021 -# Process ID: 4379 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625 -# Command line: vivado -mode batch -source axi_ad9625_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625/vivado.jou -#----------------------------------------------------------- -source axi_ad9625_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9625 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9625 [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9625_pnmon.v" \ -# "axi_ad9625_channel.v" \ -# "axi_ad9625_if.v" \ -# "axi_ad9625.v" ] -# adi_ip_properties axi_ad9625 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_100' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_101' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_102' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_103' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_104' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_105' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_106' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_107' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_108' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_109' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_110' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_111' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_112' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_113' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_114' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_115' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_116' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_117' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_118' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_119' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_120' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_121' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_122' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_123' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_124' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_125' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_126' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_127' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_128' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_129' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_130' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_131' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_132' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_133' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_134' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_135' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_136' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_137' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_138' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_139' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_140' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_141' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_142' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_143' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_144' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_145' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_146' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_147' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_148' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_149' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_150' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_151' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_152' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_153' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_154' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_155' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_156' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_157' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_158' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_159' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_160' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_161' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_162' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_163' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_164' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_165' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_166' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_167' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_168' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_169' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_170' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_171' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_172' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_173' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_174' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_175' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_176' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_177' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_178' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_179' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_180' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_181' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_182' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_183' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_184' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_185' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_186' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_187' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_188' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_128': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_129': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_130': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_131': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_132': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_133': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_134': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_135': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_136': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_137': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_138': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_139': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_140': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_141': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_142': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_143': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_144': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_145': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_146': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_147': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_148': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_149': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_150': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_151': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_152': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_153': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_154': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_155': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_156': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_157': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_158': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_159': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_160': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_161': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_162': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_163': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_164': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_165': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_166': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_167': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_168': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_169': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_170': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_171': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_172': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_173': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_174': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_175': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_176': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_177': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_178': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_179': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_180': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_181': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_182': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_183': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_184': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_185': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_186': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_187': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_188': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_189': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_190': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_191': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_192': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_193': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_194': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_195': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_196': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_197': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_198': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_199': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_200': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_201': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_202': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_203': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_204': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_205': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_206': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_207': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_208': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_209': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_210': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_211': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_212': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_213': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_214': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_215': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_216': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_217': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_218': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_219': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_220': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_221': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_222': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_223': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_224': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_225': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_226': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_227': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_228': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_229': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_230': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_231': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_232': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_233': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_234': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_235': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_236': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_237': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_238': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_239': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_240': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_241': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_242': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_243': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_244': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_245': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_246': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_247': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_248': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_249': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_250': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_251': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_252': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_253': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_254': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_255': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_128': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_129': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_130': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_131': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_132': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_133': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_134': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_135': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_136': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_137': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_138': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_139': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_140': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_141': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_142': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_143': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_144': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_145': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_146': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_147': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_148': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_149': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_150': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_151': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_152': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_153': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_154': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_155': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_156': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_157': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_158': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_159': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_160': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_161': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_162': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_163': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_164': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_165': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_166': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_167': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_168': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_169': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_170': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_171': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_172': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_173': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_174': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_175': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_176': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_177': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_178': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_179': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_180': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_181': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_182': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_183': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_184': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_185': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_186': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_187': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_188': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_189': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_190': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_191': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_192': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_193': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_194': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_195': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_196': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_197': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_198': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_199': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_200': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_201': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_202': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_203': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_204': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_205': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_206': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_207': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_208': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_209': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_210': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_211': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_212': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_213': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_214': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_215': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_216': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_217': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_218': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_219': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_220': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_221': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_222': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_223': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_224': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_225': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_226': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_227': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_228': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_229': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_230': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_231': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_232': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_233': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_234': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_235': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_236': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_237': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_238': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_239': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_240': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_241': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_242': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_243': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_244': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_245': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_246': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_247': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_248': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_249': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_250': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_251': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_252': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_253': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_254': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_255': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9625 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:11:10 2021... diff --git a/adi_library/axi_ad9671/axi_ad9671_ip.log b/adi_library/axi_ad9671/axi_ad9671_ip.log deleted file mode 100644 index 06e1f07e..00000000 --- a/adi_library/axi_ad9671/axi_ad9671_ip.log +++ /dev/null @@ -1,1543 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9671_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9671 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9671 [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9671_pnmon.v" \ -# "axi_ad9671_channel.v" \ -# "axi_ad9671_if.v" \ -# "axi_ad9671.v" ] -# adi_ip_properties axi_ad9671 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((64 * QUAD_OR_DUAL_N) + 63):0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_100' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_101' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_102' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_103' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_104' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_105' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_106' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_107' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_108' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_109' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_110' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_111' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_112' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_113' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_114' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_115' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_116' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_117' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_118' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_119' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_120' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_121' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_122' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_123' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_124' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_125' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_126' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_127' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_64' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_65' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_66' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_67' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_68' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_69' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_70' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_71' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_72' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_73' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((64 * QUAD_OR_DUAL_N) + 63):0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_sync_out' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9371 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]] -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:11:27 2021... diff --git a/adi_library/axi_ad9671/vivado.jou b/adi_library/axi_ad9671/vivado.jou deleted file mode 100644 index 18a73350..00000000 --- a/adi_library/axi_ad9671/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:11:11 2021 -# Process ID: 4469 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671 -# Command line: vivado -mode batch -source axi_ad9671_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671/vivado.jou -#----------------------------------------------------------- -source axi_ad9671_ip.tcl diff --git a/adi_library/axi_ad9671/vivado.log b/adi_library/axi_ad9671/vivado.log deleted file mode 100644 index faeb6383..00000000 --- a/adi_library/axi_ad9671/vivado.log +++ /dev/null @@ -1,1548 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:11:11 2021 -# Process ID: 4469 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671 -# Command line: vivado -mode batch -source axi_ad9671_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671/vivado.jou -#----------------------------------------------------------- -source axi_ad9671_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9671 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9671 [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9671_pnmon.v" \ -# "axi_ad9671_channel.v" \ -# "axi_ad9671_if.v" \ -# "axi_ad9671.v" ] -# adi_ip_properties axi_ad9671 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((64 * QUAD_OR_DUAL_N) + 63):0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_100' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_101' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_102' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_103' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_104' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_105' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_106' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_107' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_108' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_109' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_110' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_111' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_112' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_113' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_114' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_115' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_116' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_117' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_118' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_119' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_120' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_121' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_122' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_123' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_124' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_125' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_126' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_127' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_64' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_65' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_66' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_67' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_68' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_69' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_70' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_71' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_72' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_73' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((64 * QUAD_OR_DUAL_N) + 63):0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_sync_out' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9371 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]] -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:11:27 2021... diff --git a/adi_library/axi_ad9680/axi_ad9680_ip.log b/adi_library/axi_ad9680/axi_ad9680_ip.log deleted file mode 100644 index 6cd2bf2a..00000000 --- a/adi_library/axi_ad9680/axi_ad9680_ip.log +++ /dev/null @@ -1,1631 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9680_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9680 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9680'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9680 [list \ -# "axi_ad9680.v" ] -# adi_ip_properties axi_ad9680 -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9680 "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \ -# } -# set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:11:35 2021... diff --git a/adi_library/axi_ad9680/vivado.jou b/adi_library/axi_ad9680/vivado.jou deleted file mode 100644 index 8dec1908..00000000 --- a/adi_library/axi_ad9680/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:11:27 2021 -# Process ID: 4559 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9680 -# Command line: vivado -mode batch -source axi_ad9680_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9680/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9680/vivado.jou -#----------------------------------------------------------- -source axi_ad9680_ip.tcl diff --git a/adi_library/axi_ad9680/vivado.log b/adi_library/axi_ad9680/vivado.log deleted file mode 100644 index 5f21f1fa..00000000 --- a/adi_library/axi_ad9680/vivado.log +++ /dev/null @@ -1,1636 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:11:27 2021 -# Process ID: 4559 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9680 -# Command line: vivado -mode batch -source axi_ad9680_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9680/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9680/vivado.jou -#----------------------------------------------------------- -source axi_ad9680_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9680 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9680'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9680 [list \ -# "axi_ad9680.v" ] -# adi_ip_properties axi_ad9680 -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9680 "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \ -# } -# set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:11:35 2021... diff --git a/adi_library/axi_ad9684/axi_ad9684_ip.log b/adi_library/axi_ad9684/axi_ad9684_ip.log deleted file mode 100644 index a4705c65..00000000 --- a/adi_library/axi_ad9684/axi_ad9684_ip.log +++ /dev/null @@ -1,1426 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9684_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9684 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9684 [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9684_pnmon.v" \ -# "axi_ad9684_if.v" \ -# "axi_ad9684_channel.v" \ -# "axi_ad9684_constr.xdc" \ -# "axi_ad9684.v" ] -# adi_ip_properties axi_ad9684 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_or_n' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_or_p' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_or_n': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_or_p': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9684 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_in_p' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_in_n' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk_in_p': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:11:52 2021... diff --git a/adi_library/axi_ad9684/vivado.jou b/adi_library/axi_ad9684/vivado.jou deleted file mode 100644 index 8a40f24f..00000000 --- a/adi_library/axi_ad9684/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:11:35 2021 -# Process ID: 4617 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684 -# Command line: vivado -mode batch -source axi_ad9684_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684/vivado.jou -#----------------------------------------------------------- -source axi_ad9684_ip.tcl diff --git a/adi_library/axi_ad9684/vivado.log b/adi_library/axi_ad9684/vivado.log deleted file mode 100644 index 4ebc6514..00000000 --- a/adi_library/axi_ad9684/vivado.log +++ /dev/null @@ -1,1431 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:11:35 2021 -# Process ID: 4617 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684 -# Command line: vivado -mode batch -source axi_ad9684_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684/vivado.jou -#----------------------------------------------------------- -source axi_ad9684_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9684 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9684 [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9684_pnmon.v" \ -# "axi_ad9684_if.v" \ -# "axi_ad9684_channel.v" \ -# "axi_ad9684_constr.xdc" \ -# "axi_ad9684.v" ] -# adi_ip_properties axi_ad9684 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_clk.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9684'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_n_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in_p_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_or_n' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_or_p' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'adc_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_n_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in_p_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_or_n': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_or_p': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9684 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_in_p' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_in_n' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk_in_p': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:11:52 2021... diff --git a/adi_library/axi_ad9739a/axi_ad9739a_ip.log b/adi_library/axi_ad9739a/axi_ad9739a_ip.log deleted file mode 100644 index 65391dfe..00000000 --- a/adi_library/axi_ad9739a/axi_ad9739a_ip.log +++ /dev/null @@ -1,1351 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9739a_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9739a -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9739a [list \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9739a_channel.v" \ -# "axi_ad9739a_core.v" \ -# "axi_ad9739a_if.v" \ -# "axi_ad9739a.v" ] -# adi_ip_properties axi_ad9739a -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_div_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_div_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_div_clk': FREQ_HZ bus parameter is missing for output clock interface. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9739a "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:12:11 2021... diff --git a/adi_library/axi_ad9739a/vivado.jou b/adi_library/axi_ad9739a/vivado.jou deleted file mode 100644 index 59f4893e..00000000 --- a/adi_library/axi_ad9739a/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:11:53 2021 -# Process ID: 4705 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a -# Command line: vivado -mode batch -source axi_ad9739a_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a/vivado.jou -#----------------------------------------------------------- -source axi_ad9739a_ip.tcl diff --git a/adi_library/axi_ad9739a/vivado.log b/adi_library/axi_ad9739a/vivado.log deleted file mode 100644 index 1c583594..00000000 --- a/adi_library/axi_ad9739a/vivado.log +++ /dev/null @@ -1,1356 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:11:53 2021 -# Process ID: 4705 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a -# Command line: vivado -mode batch -source axi_ad9739a_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a/vivado.jou -#----------------------------------------------------------- -source axi_ad9739a_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9739a -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9739a [list \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_ad9739a_channel.v" \ -# "axi_ad9739a_core.v" \ -# "axi_ad9739a_if.v" \ -# "axi_ad9739a.v" ] -# adi_ip_properties axi_ad9739a -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9739a'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_n_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_a_p_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_n_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out_b_p_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_a_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'dac_out_b_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_div_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_n_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_a_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a_p_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_n' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_n_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_out_b_p' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b_p_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_div_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_div_clk': FREQ_HZ bus parameter is missing for output clock interface. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9739a "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:12:11 2021... diff --git a/adi_library/axi_ad9963/axi_ad9963_ip.log b/adi_library/axi_ad9963/axi_ad9963_ip.log deleted file mode 100644 index 190c9d62..00000000 --- a/adi_library/axi_ad9963/axi_ad9963_ip.log +++ /dev/null @@ -1,1449 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_ad9963_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9963 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9963 [list \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_iqcor.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "axi_ad9963_constr.xdc" \ -# "axi_ad9963_if.v" \ -# "axi_ad9963_rx_pnmon.v" \ -# "axi_ad9963_rx_channel.v" \ -# "axi_ad9963_rx.v" \ -# "axi_ad9963_tx_channel.v" \ -# "axi_ad9963_tx.v" \ -# "axi_ad9963.v" ] -# adi_ip_properties axi_ad9963 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_i'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_q'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'trx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_in' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'trx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_i'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_q'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'trx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'trx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_sync_out' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_valid_i' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_i': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_i': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_valid_q' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_q': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_q': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'trx_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'tx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9963 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# adi_set_ports_dependency "delay_clk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.ADC_IODELAY_ENABLE')) = 1)" 0 -# ipx::infer_bus_interface trx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -# ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:12:36 2021... diff --git a/adi_library/axi_ad9963/vivado.jou b/adi_library/axi_ad9963/vivado.jou deleted file mode 100644 index b43dc43b..00000000 --- a/adi_library/axi_ad9963/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:12:12 2021 -# Process ID: 4797 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963 -# Command line: vivado -mode batch -source axi_ad9963_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963/vivado.jou -#----------------------------------------------------------- -source axi_ad9963_ip.tcl diff --git a/adi_library/axi_ad9963/vivado.log b/adi_library/axi_ad9963/vivado.log deleted file mode 100644 index c644ccae..00000000 --- a/adi_library/axi_ad9963/vivado.log +++ /dev/null @@ -1,1454 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:12:12 2021 -# Process ID: 4797 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963 -# Command line: vivado -mode batch -source axi_ad9963_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963/vivado.jou -#----------------------------------------------------------- -source axi_ad9963_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_ad9963 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_ad9963 [list \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_iqcor.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "axi_ad9963_constr.xdc" \ -# "axi_ad9963_if.v" \ -# "axi_ad9963_rx_pnmon.v" \ -# "axi_ad9963_rx_channel.v" \ -# "axi_ad9963_rx.v" \ -# "axi_ad9963_tx_channel.v" \ -# "axi_ad9963_tx.v" \ -# "axi_ad9963.v" ] -# adi_ip_properties axi_ad9963 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_i'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_q'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'trx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_in' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_out' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'trx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_i'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_q'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'trx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'trx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_sync_out' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'trx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_valid_i' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_i': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_i': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_valid_q' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_q': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_q': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'trx_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'tx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_ad9963 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# adi_set_ports_dependency "delay_clk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.ADC_IODELAY_ENABLE')) = 1)" 0 -# ipx::infer_bus_interface trx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'trx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -# ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:12:36 2021... diff --git a/adi_library/axi_adc_decimate/axi_adc_decimate_ip.log b/adi_library/axi_adc_decimate/axi_adc_decimate_ip.log deleted file mode 100644 index 8e505cee..00000000 --- a/adi_library/axi_adc_decimate/axi_adc_decimate_ip.log +++ /dev/null @@ -1,1308 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_adc_decimate_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_adc_decimate -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_adc_decimate [list \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/ad_iqcor.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "fir_decim.v" \ -# "cic_decim.v" \ -# "axi_adc_decimate_filter.v" \ -# "axi_adc_decimate_reg.v" \ -# "axi_adc_decimate.v" ] -# adi_ip_properties axi_adc_decimate -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_dec_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_dec_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'adc_rate'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_oversampling' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rate_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rate_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rate_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'adc_rate'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'adc_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_dec_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_dec_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'adc_rate'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'adc_rate'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_oversampling_en' and definition port 'EN'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_oversampling': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_rate' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rate_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_rate' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rate_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_rate' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rate_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_valid_a' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_valid_b' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cic:1.0 \ -# } -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:12:55 2021... diff --git a/adi_library/axi_adc_decimate/vivado.jou b/adi_library/axi_adc_decimate/vivado.jou deleted file mode 100644 index e42741ae..00000000 --- a/adi_library/axi_adc_decimate/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:12:43 2021 -# Process ID: 4960 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate -# Command line: vivado -mode batch -source axi_adc_decimate_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate/vivado.jou -#----------------------------------------------------------- -source axi_adc_decimate_ip.tcl diff --git a/adi_library/axi_adc_decimate/vivado.log b/adi_library/axi_adc_decimate/vivado.log deleted file mode 100644 index 5d619a23..00000000 --- a/adi_library/axi_adc_decimate/vivado.log +++ /dev/null @@ -1,1313 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:12:43 2021 -# Process ID: 4960 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate -# Command line: vivado -mode batch -source axi_adc_decimate_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate/vivado.jou -#----------------------------------------------------------- -source axi_adc_decimate_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_adc_decimate -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_adc_decimate [list \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/ad_iqcor.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "fir_decim.v" \ -# "cic_decim.v" \ -# "axi_adc_decimate_filter.v" \ -# "axi_adc_decimate_reg.v" \ -# "axi_adc_decimate.v" ] -# adi_ip_properties axi_adc_decimate -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_decimate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_dec_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_dec_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'adc_rate'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_a_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_b_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_a_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_dec_b_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_oversampling' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rate_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rate_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rate_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'adc_rate'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'adc_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_dec_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_dec_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'adc_rate'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'adc_rate'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_dec_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_oversampling_en' and definition port 'EN'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_oversampling': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_rate' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rate_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_rate' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rate_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_rate' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rate_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_valid_a' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_valid_b' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_dec_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cic:1.0 \ -# } -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:12:55 2021... diff --git a/adi_library/axi_adc_trigger/axi_adc_trigger_ip.log b/adi_library/axi_adc_trigger/axi_adc_trigger_ip.log deleted file mode 100644 index 17ff6e80..00000000 --- a/adi_library/axi_adc_trigger/axi_adc_trigger_ip.log +++ /dev/null @@ -1,1036 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_adc_trigger_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_adc_trigger -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_adc_trigger [list \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "axi_adc_trigger_constr.xdc" \ -# "axi_adc_trigger_reg.v" \ -# "axi_adc_trigger.v" ] -# adi_ip_properties axi_adc_trigger -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'data_a_cmp' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'data_b_cmp' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'limit_a_cmp' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'limit_b_cmp' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'hyst_a_high_limit' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'hyst_a_low_limit' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'hyst_b_high_limit' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'hyst_b_low_limit' has a dependency on the module local parameter or undefined parameter 'DW'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data_a' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data_a_trig' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data_b' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data_b_trig' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data_valid_a' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_a': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_a_trig': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_a_trig': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data_valid_b' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_b': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_b_trig': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_b_trig': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:13:04 2021... diff --git a/adi_library/axi_adc_trigger/vivado.jou b/adi_library/axi_adc_trigger/vivado.jou deleted file mode 100644 index 5f62f4bd..00000000 --- a/adi_library/axi_adc_trigger/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:12:55 2021 -# Process ID: 5029 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger -# Command line: vivado -mode batch -source axi_adc_trigger_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger/vivado.jou -#----------------------------------------------------------- -source axi_adc_trigger_ip.tcl diff --git a/adi_library/axi_adc_trigger/vivado.log b/adi_library/axi_adc_trigger/vivado.log deleted file mode 100644 index d34a1b91..00000000 --- a/adi_library/axi_adc_trigger/vivado.log +++ /dev/null @@ -1,1041 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:12:55 2021 -# Process ID: 5029 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger -# Command line: vivado -mode batch -source axi_adc_trigger_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger/vivado.jou -#----------------------------------------------------------- -source axi_adc_trigger_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_adc_trigger -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_adc_trigger [list \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "axi_adc_trigger_constr.xdc" \ -# "axi_adc_trigger_reg.v" \ -# "axi_adc_trigger.v" ] -# adi_ip_properties axi_adc_trigger -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'data_a_cmp' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'data_b_cmp' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'limit_a_cmp' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'limit_b_cmp' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'hyst_a_high_limit' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'hyst_a_low_limit' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'hyst_b_high_limit' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'hyst_b_low_limit' has a dependency on the module local parameter or undefined parameter 'DW'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data_a' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data_a_trig' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data_b' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data_b_trig' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data_valid_a' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_a': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_a_trig': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_a_trig': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data_valid_b' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_b': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_b_trig': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_b_trig': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:13:04 2021... diff --git a/adi_library/axi_adrv9001/axi_adrv9001_ip.log b/adi_library/axi_adrv9001/axi_adrv9001_ip.log deleted file mode 100644 index 9a16d61f..00000000 --- a/adi_library/axi_adrv9001/axi_adrv9001_ip.log +++ /dev/null @@ -1,1713 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_adrv9001_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_adrv9001 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_adrv9001 [list \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \ -# "$ad_hdl_dir/library/common/ad_tdd_control.v" \ -# "$ad_hdl_dir/library/common/ad_addsub.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/ad_pngen.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "adrv9001_rx.v" \ -# "adrv9001_tx.v" \ -# "adrv9001_pack.v" \ -# "adrv9001_aligner4.v" \ -# "adrv9001_aligner8.v" \ -# "adrv9001_rx_link.v" \ -# "adrv9001_tx_link.v" \ -# "axi_adrv9001_rx.v" \ -# "axi_adrv9001_rx_channel.v" \ -# "axi_adrv9001_if.v" \ -# "axi_adrv9001_tx.v" \ -# "axi_adrv9001_tx_channel.v" \ -# "axi_adrv9001_core.v" \ -# "axi_adrv9001_constr.xdc" \ -# "axi_adrv9001_tdd.v" \ -# "axi_adrv9001.v" ] -# adi_ip_properties axi_adrv9001 -WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_clk.v'. -WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v'. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_addsub.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pngen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_tdd_control.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_tdd_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_addsub.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pngen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_tdd_control.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_tdd_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx1_dld' has a dependency on the module local parameter or undefined parameter 'NUM_LANES'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx1_dwdata' has a dependency on the module local parameter or undefined parameter 'DRP_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx1_dwdata' has a dependency on the module local parameter or undefined parameter 'NUM_LANES'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx1_drdata' has a dependency on the module local parameter or undefined parameter 'DRP_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx1_drdata' has a dependency on the module local parameter or undefined parameter 'NUM_LANES'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx2_dld' has a dependency on the module local parameter or undefined parameter 'NUM_LANES'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx2_dwdata' has a dependency on the module local parameter or undefined parameter 'DRP_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx2_dwdata' has a dependency on the module local parameter or undefined parameter 'NUM_LANES'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx2_drdata' has a dependency on the module local parameter or undefined parameter 'DRP_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx2_drdata' has a dependency on the module local parameter or undefined parameter 'NUM_LANES'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_2_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_2_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_2_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_2_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_2_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_2_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_2_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_2_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_1_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_1_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_2_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_2_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'dac_1_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_1_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'dac_2_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_2_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'mssi': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'mssi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tdd_sync_cntr' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd_cntr': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd_cntr': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_1_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_1_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_2_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_2_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_1_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_1_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_2_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_2_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ref_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_adrv9001 "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# } -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_1_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_2_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_1_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_2_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_2_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_1_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_1_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_1_rst'. -# ipx::infer_bus_interface adc_2_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_2_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_2_rst'. -# ipx::infer_bus_interface dac_1_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dac_1_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_1_rst'. -# ipx::infer_bus_interface dac_2_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_2_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dac_2_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_2_rst'. -# ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces adc_1_rst -of_objects [ipx::current_core]] -# ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces adc_2_rst -of_objects [ipx::current_core]] -# ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces dac_1_rst -of_objects [ipx::current_core]] -# ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces dac_2_rst -of_objects [ipx::current_core]] -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:13:37 2021... diff --git a/adi_library/axi_adrv9001/vivado.jou b/adi_library/axi_adrv9001/vivado.jou deleted file mode 100644 index 8530b352..00000000 --- a/adi_library/axi_adrv9001/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:13:05 2021 -# Process ID: 5093 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001 -# Command line: vivado -mode batch -source axi_adrv9001_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001/vivado.jou -#----------------------------------------------------------- -source axi_adrv9001_ip.tcl diff --git a/adi_library/axi_adrv9001/vivado.log b/adi_library/axi_adrv9001/vivado.log deleted file mode 100644 index ae1f392c..00000000 --- a/adi_library/axi_adrv9001/vivado.log +++ /dev/null @@ -1,1718 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:13:05 2021 -# Process ID: 5093 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001 -# Command line: vivado -mode batch -source axi_adrv9001_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001/vivado.jou -#----------------------------------------------------------- -source axi_adrv9001_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_adrv9001 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_adrv9001 [list \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \ -# "$ad_hdl_dir/library/common/ad_tdd_control.v" \ -# "$ad_hdl_dir/library/common/ad_addsub.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/ad_pngen.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "adrv9001_rx.v" \ -# "adrv9001_tx.v" \ -# "adrv9001_pack.v" \ -# "adrv9001_aligner4.v" \ -# "adrv9001_aligner8.v" \ -# "adrv9001_rx_link.v" \ -# "adrv9001_tx_link.v" \ -# "axi_adrv9001_rx.v" \ -# "axi_adrv9001_rx_channel.v" \ -# "axi_adrv9001_if.v" \ -# "axi_adrv9001_tx.v" \ -# "axi_adrv9001_tx_channel.v" \ -# "axi_adrv9001_core.v" \ -# "axi_adrv9001_constr.xdc" \ -# "axi_adrv9001_tdd.v" \ -# "axi_adrv9001.v" ] -# adi_ip_properties axi_adrv9001 -WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_clk.v'. -WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v'. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_addsub.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pngen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_tdd_control.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_tdd_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_addsub.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pngen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_in.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_serdes_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_tdd_control.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_tdd_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9001'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx1_dld' has a dependency on the module local parameter or undefined parameter 'NUM_LANES'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx1_dwdata' has a dependency on the module local parameter or undefined parameter 'DRP_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx1_dwdata' has a dependency on the module local parameter or undefined parameter 'NUM_LANES'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx1_drdata' has a dependency on the module local parameter or undefined parameter 'DRP_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx1_drdata' has a dependency on the module local parameter or undefined parameter 'NUM_LANES'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx2_dld' has a dependency on the module local parameter or undefined parameter 'NUM_LANES'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx2_dwdata' has a dependency on the module local parameter or undefined parameter 'DRP_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx2_dwdata' has a dependency on the module local parameter or undefined parameter 'NUM_LANES'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx2_drdata' has a dependency on the module local parameter or undefined parameter 'DRP_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_rx2_drdata' has a dependency on the module local parameter or undefined parameter 'NUM_LANES'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_2_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_2_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_2_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_2_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_i1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_q1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_q0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_1_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_2_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_2_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_1_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_2_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_2_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_1_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_1_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_2_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_2_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'dac_1_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_1_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'dac_2_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_2_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'mssi': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'mssi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tdd_sync_cntr' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd_cntr': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tdd_cntr': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_1_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_1_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_1_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_1_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_2_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_2_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_1_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_1_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_2_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'adc_2_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_1_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_1_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_2_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'dac_2_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ref_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_adrv9001 "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# } -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_1_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_2_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_1_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_2_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_2_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_1_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_1_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_1_rst'. -# ipx::infer_bus_interface adc_2_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_2_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_2_rst'. -# ipx::infer_bus_interface dac_1_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dac_1_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_1_rst'. -# ipx::infer_bus_interface dac_2_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_2_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dac_2_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_2_rst'. -# ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces adc_1_rst -of_objects [ipx::current_core]] -# ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces adc_2_rst -of_objects [ipx::current_core]] -# ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces dac_1_rst -of_objects [ipx::current_core]] -# ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces dac_2_rst -of_objects [ipx::current_core]] -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:13:37 2021... diff --git a/adi_library/axi_adrv9009/axi_adrv9009_ip.log b/adi_library/axi_adrv9009/axi_adrv9009_ip.log deleted file mode 100644 index c637c7fd..00000000 --- a/adi_library/axi_adrv9009/axi_adrv9009_ip.log +++ /dev/null @@ -1,2268 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_adrv9009_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_adrv9009 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_adrv9009 [list \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_iqcor.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ -# "axi_adrv9009_if.v" \ -# "axi_adrv9009_rx_channel.v" \ -# "axi_adrv9009_rx.v" \ -# "axi_adrv9009_rx_os.v" \ -# "axi_adrv9009_tx_channel.v" \ -# "axi_adrv9009_tx.v" \ -# "axi_adrv9009.v" ] -# adi_ip_properties axi_adrv9009 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx_os'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'dac_tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx_os'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'dac_tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_sync_out' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_os_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_os_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_os_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_adrv9009 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *adc_rx_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *adc_rx_os_valid* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_os_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:14:01 2021... diff --git a/adi_library/axi_adrv9009/vivado.jou b/adi_library/axi_adrv9009/vivado.jou deleted file mode 100644 index 513c2bfb..00000000 --- a/adi_library/axi_adrv9009/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:13:38 2021 -# Process ID: 5235 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009 -# Command line: vivado -mode batch -source axi_adrv9009_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009/vivado.jou -#----------------------------------------------------------- -source axi_adrv9009_ip.tcl diff --git a/adi_library/axi_adrv9009/vivado.log b/adi_library/axi_adrv9009/vivado.log deleted file mode 100644 index c3f9e8ca..00000000 --- a/adi_library/axi_adrv9009/vivado.log +++ /dev/null @@ -1,2273 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:13:38 2021 -# Process ID: 5235 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009 -# Command line: vivado -mode batch -source axi_adrv9009_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009/vivado.jou -#----------------------------------------------------------- -source axi_adrv9009_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_adrv9009 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_adrv9009 [list \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/ad_iqcor.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ -# "axi_adrv9009_if.v" \ -# "axi_adrv9009_rx_channel.v" \ -# "axi_adrv9009_rx.v" \ -# "axi_adrv9009_rx_os.v" \ -# "axi_adrv9009_tx_channel.v" \ -# "axi_adrv9009_tx.v" \ -# "axi_adrv9009.v" ] -# adi_ip_properties axi_adrv9009 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adrv9009'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx_os'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'dac_tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_i1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_q0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'adc_os_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'adc_rx_os'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dac_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '127:0' is present in all ports of the interface 'dac_tx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_os_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_sync_out' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_tx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_os_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_os_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_rx_os_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_rx_os': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_tx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_os_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_adrv9009 "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *adc_rx_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *adc_rx_os_valid* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_os_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_os_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:14:01 2021... diff --git a/adi_library/axi_clkgen/axi_clkgen_ip.log b/adi_library/axi_clkgen/axi_clkgen_ip.log deleted file mode 100644 index b63678fb..00000000 --- a/adi_library/axi_clkgen/axi_clkgen_ip.log +++ /dev/null @@ -1,751 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_clkgen_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_clkgen -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_clkgen [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_clkgen.v" \ -# "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \ -# "bd/bd.tcl" \ -# "axi_clkgen.v" ] -# adi_ip_properties axi_clkgen -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clkgen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clkgen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Synthesis'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Synthesis'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Simulation'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Simulation'. -Resolution: Remove the file from the specified file group. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_bd axi_clkgen "bd/bd.tcl" -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk2' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_0' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_1' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# set cc [ipx::current_core] -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set param [ipx::add_user_parameter ENABLE_CLKIN2 $cc] -# set_property -dict {value_resolve_type user value_format bool value false} $param -# set param [ipgui::add_param -name {ENABLE_CLKIN2} -component $cc -parent $page0] -# set_property -dict [list \ -# display_name {Enable secondary clock input} \ -# widget {checkBox} \ -# ] $param -# set param [ipx::add_user_parameter ENABLE_CLKOUT1 $cc] -# set_property -dict {value_resolve_type user value_format bool value false} $param -# set param [ipgui::add_param -name {ENABLE_CLKOUT1} -component $cc -parent $page0] -# set_property -dict [list \ -# display_name {Enable secondary clock output} \ -# widget {checkBox} \ -# ] $param -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# set_property enablement_tcl_expr {$ENABLE_CLKIN2} [ipx::get_user_parameters CLKIN2_PERIOD -of_objects $cc] -# set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_DIV -of_objects $cc] -# set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_PHASE -of_objects $cc] -# adi_set_ports_dependency clk2 ENABLE_CLKIN2 0 -# adi_set_ports_dependency clk_1 ENABLE_CLKOUT1 -# ipx::create_xgui_files $cc -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:22:17 2021... diff --git a/adi_library/axi_clkgen/vivado.jou b/adi_library/axi_clkgen/vivado.jou deleted file mode 100644 index 35019320..00000000 --- a/adi_library/axi_clkgen/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:22:07 2021 -# Process ID: 66374 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen -# Command line: vivado -mode batch -source axi_clkgen_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen/vivado.jou -#----------------------------------------------------------- -source axi_clkgen_ip.tcl diff --git a/adi_library/axi_clkgen/vivado.log b/adi_library/axi_clkgen/vivado.log deleted file mode 100644 index b5767b54..00000000 --- a/adi_library/axi_clkgen/vivado.log +++ /dev/null @@ -1,756 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:22:07 2021 -# Process ID: 66374 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen -# Command line: vivado -mode batch -source axi_clkgen_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen/vivado.jou -#----------------------------------------------------------- -source axi_clkgen_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_clkgen -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_clkgen [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_clkgen.v" \ -# "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \ -# "bd/bd.tcl" \ -# "axi_clkgen.v" ] -# adi_ip_properties axi_clkgen -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clkgen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clkgen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Synthesis'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Synthesis'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Simulation'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Simulation'. -Resolution: Remove the file from the specified file group. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_bd axi_clkgen "bd/bd.tcl" -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk2' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_0' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_1' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# set cc [ipx::current_core] -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set param [ipx::add_user_parameter ENABLE_CLKIN2 $cc] -# set_property -dict {value_resolve_type user value_format bool value false} $param -# set param [ipgui::add_param -name {ENABLE_CLKIN2} -component $cc -parent $page0] -# set_property -dict [list \ -# display_name {Enable secondary clock input} \ -# widget {checkBox} \ -# ] $param -# set param [ipx::add_user_parameter ENABLE_CLKOUT1 $cc] -# set_property -dict {value_resolve_type user value_format bool value false} $param -# set param [ipgui::add_param -name {ENABLE_CLKOUT1} -component $cc -parent $page0] -# set_property -dict [list \ -# display_name {Enable secondary clock output} \ -# widget {checkBox} \ -# ] $param -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# set_property enablement_tcl_expr {$ENABLE_CLKIN2} [ipx::get_user_parameters CLKIN2_PERIOD -of_objects $cc] -# set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_DIV -of_objects $cc] -# set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_PHASE -of_objects $cc] -# adi_set_ports_dependency clk2 ENABLE_CLKIN2 0 -# adi_set_ports_dependency clk_1 ENABLE_CLKOUT1 -# ipx::create_xgui_files $cc -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:22:17 2021... diff --git a/adi_library/axi_dac_interpolate/axi_dac_interpolate_ip.log b/adi_library/axi_dac_interpolate/axi_dac_interpolate_ip.log deleted file mode 100644 index 3554011d..00000000 --- a/adi_library/axi_dac_interpolate/axi_dac_interpolate_ip.log +++ /dev/null @@ -1,1303 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_dac_interpolate_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_dac_interpolate -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_dac_interpolate [list \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/ad_iqcor.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "axi_dac_interpolate_constr.xdc" \ -# "cic_interp.v" \ -# "fir_interp.v" \ -# "axi_dac_interpolate_reg.v" \ -# "axi_dac_interpolate_filter.v" \ -# "axi_dac_interpolate.v" ] -# adi_ip_properties axi_dac_interpolate -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_int_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_int_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_int_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_int_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_int_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_int_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_valid_a' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_valid_b' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_valid_a' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_a': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_valid_b' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_b': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:14:13 2021... diff --git a/adi_library/axi_dac_interpolate/vivado.jou b/adi_library/axi_dac_interpolate/vivado.jou deleted file mode 100644 index 8098908d..00000000 --- a/adi_library/axi_dac_interpolate/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:14:02 2021 -# Process ID: 5353 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate -# Command line: vivado -mode batch -source axi_dac_interpolate_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate/vivado.jou -#----------------------------------------------------------- -source axi_dac_interpolate_ip.tcl diff --git a/adi_library/axi_dac_interpolate/vivado.log b/adi_library/axi_dac_interpolate/vivado.log deleted file mode 100644 index ebed4960..00000000 --- a/adi_library/axi_dac_interpolate/vivado.log +++ /dev/null @@ -1,1308 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:14:02 2021 -# Process ID: 5353 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate -# Command line: vivado -mode batch -source axi_dac_interpolate_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate/vivado.jou -#----------------------------------------------------------- -source axi_dac_interpolate_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_dac_interpolate -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_dac_interpolate [list \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/ad_iqcor.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "axi_dac_interpolate_constr.xdc" \ -# "cic_interp.v" \ -# "fir_interp.v" \ -# "axi_dac_interpolate_reg.v" \ -# "axi_dac_interpolate_filter.v" \ -# "axi_dac_interpolate.v" ] -# adi_ip_properties axi_dac_interpolate -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dac_interpolate'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_int_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_int_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_a' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_b' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_a' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_int_b' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_int_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_int_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_int_a'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_int_b'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_int_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_a' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_valid_a' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_b' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_valid_b' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_a': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_int_b': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_valid_a' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_a': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_a': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_valid_b' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_b': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma_b': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:14:13 2021... diff --git a/adi_library/axi_dmac/axi_dmac_ip.log b/adi_library/axi_dmac/axi_dmac_ip.log deleted file mode 100644 index 18e6cfa0..00000000 --- a/adi_library/axi_dmac/axi_dmac_ip.log +++ /dev/null @@ -1,1122 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_dmac_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_dmac -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_dmac [list \ -# "$ad_hdl_dir/library/common/ad_mem_asym.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "inc_id.vh" \ -# "resp.vh" \ -# "axi_dmac_burst_memory.v" \ -# "axi_dmac_regmap.v" \ -# "axi_dmac_regmap_request.v" \ -# "axi_dmac_reset_manager.v" \ -# "axi_dmac_resize_dest.v" \ -# "axi_dmac_resize_src.v" \ -# "axi_dmac_response_manager.v" \ -# "axi_dmac_transfer.v" \ -# "address_generator.v" \ -# "data_mover.v" \ -# "request_arb.v" \ -# "request_generator.v" \ -# "response_handler.v" \ -# "axi_register_slice.v" \ -# "2d_transfer.v" \ -# "dest_axi_mm.v" \ -# "dest_axi_stream.v" \ -# "dest_fifo_inf.v" \ -# "src_axi_mm.v" \ -# "src_axi_stream.v" \ -# "src_fifo_inf.v" \ -# "splitter.v" \ -# "response_generator.v" \ -# "axi_dmac.v" \ -# "axi_dmac_constr.ttcl" \ -# "axi_dmac_pkg_sv.ttcl" \ -# "bd/bd.tcl" ] -# adi_ip_properties axi_dmac -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac/axi_dmac_constr.ttcl' ignored by IP packager. -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac/axi_dmac_pkg_sv.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dest_request_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dest_data_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dest_address_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dest_response_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'src_request_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'src_data_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'src_address_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'src_response_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_req_measured_burst_length' has a dependency on the module local parameter or undefined parameter 'BYTES_PER_BURST_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_dma_req_dest_address' has a dependency on the module local parameter or undefined parameter 'BYTES_PER_BEAT_WIDTH_DEST'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_dma_req_src_address' has a dependency on the module local parameter or undefined parameter 'BYTES_PER_BEAT_WIDTH_SRC'. -INFO: [IP_Flow 19-1842] HDL Parser: Found include file "inc_id.vh" from the top-level HDL file. -INFO: [IP_Flow 19-1842] HDL Parser: Found include file "resp.vh" from the top-level HDL file. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_dest_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_src_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_dest_axi_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_src_axi_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'fifo_rd_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'fifo_wr_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'm_axis_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axis_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Synthesis'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Simulation'. -Resolution: Remove the file from the specified file group. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_infer_mm_interfaces axi_dmac -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'. -INFO: [IP_Flow 19-3164] Bus Interface 'm_dest_axi': References existing address space 'm_dest_axi'. -INFO: [IP_Flow 19-3164] Bus Interface 'm_src_axi': References existing address space 'm_src_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_dest_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_src_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_dest_axi_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_src_axi_aresetn'. -# adi_ip_ttcl axi_dmac "axi_dmac_constr.ttcl" -# adi_ip_sim_ttcl axi_dmac "axi_dmac_pkg_sv.ttcl" -# adi_ip_bd axi_dmac "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_axis_fifo:1.0 \ -# analog.com:user:util_cdc:1.0 \ -# } -# set_property display_name "ADI AXI DMA Controller" [ipx::current_core] -# set_property description "ADI AXI DMA Controller" [ipx::current_core] -# adi_add_bus "s_axis" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"s_axis_ready" "TREADY"} \ -# {"s_axis_valid" "TVALID"} \ -# {"s_axis_data" "TDATA"} \ -# {"s_axis_strb" "TSTRB"} \ -# {"s_axis_keep" "TKEEP"} \ -# {"s_axis_user" "TUSER"} \ -# {"s_axis_id" "TID"} \ -# {"s_axis_dest" "TDEST"} \ -# {"s_axis_last" "TLAST"}] -# adi_add_bus_clock "s_axis_aclk" "s_axis" -# adi_add_bus "m_axis" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"m_axis_ready" "TREADY"} \ -# {"m_axis_valid" "TVALID"} \ -# {"m_axis_data" "TDATA"} \ -# {"m_axis_strb" "TSTRB"} \ -# {"m_axis_keep" "TKEEP"} \ -# {"m_axis_user" "TUSER"} \ -# {"m_axis_id" "TID"} \ -# {"m_axis_dest" "TDEST"} \ -# {"m_axis_last" "TLAST"}] -# adi_add_bus_clock "m_axis_aclk" "m_axis" -# adi_set_bus_dependency "m_src_axi" "m_src_axi" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 0)" -# adi_set_bus_dependency "m_dest_axi" "m_dest_axi" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 0)" -# adi_set_bus_dependency "s_axis" "s_axis" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 1)" -# adi_set_bus_dependency "m_axis" "m_axis" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 1)" -# adi_set_ports_dependency "fifo_rd" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 2)" -# adi_set_ports_dependency "dest_diag_level_bursts" \ -# "(spirit:decode(id('MODELPARAM_VALUE.ENABLE_DIAGNOSTICS_IF')) = 1)" -# set dummy_axi_ports [list \ -# "m_dest_axi_arvalid" \ -# "m_dest_axi_arready" \ -# "m_dest_axi_araddr" \ -# "m_dest_axi_arlen" \ -# "m_dest_axi_arsize" \ -# "m_dest_axi_arburst" \ -# "m_dest_axi_arcache" \ -# "m_dest_axi_arprot" \ -# "m_dest_axi_rready" \ -# "m_dest_axi_rvalid" \ -# "m_dest_axi_rresp" \ -# "m_dest_axi_rdata" \ -# "m_src_axi_awvalid" \ -# "m_src_axi_awready" \ -# "m_src_axi_awvalid" \ -# "m_src_axi_awaddr" \ -# "m_src_axi_awlen" \ -# "m_src_axi_awsize" \ -# "m_src_axi_awburst" \ -# "m_src_axi_awcache" \ -# "m_src_axi_awprot" \ -# "m_src_axi_wvalid" \ -# "m_src_axi_wready" \ -# "m_src_axi_wvalid" \ -# "m_src_axi_wdata" \ -# "m_src_axi_wstrb" \ -# "m_src_axi_wlast" \ -# "m_src_axi_bready" \ -# "m_src_axi_bvalid" \ -# "m_src_axi_bresp" \ -# ] -# lappend dummy_axi_ports \ -# "m_dest_axi_awid" \ -# "m_dest_axi_awlock" \ -# "m_dest_axi_wid" \ -# "m_dest_axi_bid" \ -# "m_dest_axi_arid" \ -# "m_dest_axi_arlock" \ -# "m_dest_axi_rid" \ -# "m_dest_axi_rlast" \ -# "m_src_axi_arid" \ -# "m_src_axi_arlock" \ -# "m_src_axi_rid" \ -# "m_src_axi_awid" \ -# "m_src_axi_awlock" \ -# "m_src_axi_wid" \ -# "m_src_axi_bid" -# foreach p $dummy_axi_ports { -# adi_set_ports_dependency $p "false" -# } -# set_property master_address_space_ref m_dest_axi \ -# [ipx::get_bus_interfaces m_dest_axi \ -# -of_objects [ipx::current_core]] -# set_property master_address_space_ref m_src_axi \ -# [ipx::get_bus_interfaces m_src_axi \ -# -of_objects [ipx::current_core]] -# adi_add_bus "fifo_wr" "slave" \ -# "analog.com:interface:fifo_wr_rtl:1.0" \ -# "analog.com:interface:fifo_wr:1.0" \ -# { \ -# {"fifo_wr_en" "EN"} \ -# {"fifo_wr_din" "DATA"} \ -# {"fifo_wr_overflow" "OVERFLOW"} \ -# {"fifo_wr_sync" "SYNC"} \ -# {"fifo_wr_xfer_req" "XFER_REQ"} \ -# } -# adi_add_bus_clock "fifo_wr_clk" "fifo_wr" -# adi_set_bus_dependency "fifo_wr" "fifo_wr" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 2)" -# adi_add_bus "fifo_rd" "slave" \ -# "analog.com:interface:fifo_rd_rtl:1.0" \ -# "analog.com:interface:fifo_rd:1.0" \ -# { -# {"fifo_rd_en" "EN"} \ -# {"fifo_rd_dout" "DATA"} \ -# {"fifo_rd_valid" "VALID"} \ -# {"fifo_rd_underflow" "UNDERFLOW"} \ -# } -# adi_add_bus_clock "fifo_rd_clk" "fifo_rd" -# adi_set_bus_dependency "fifo_rd" "fifo_rd" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 2)" -# foreach port {"m_dest_axi_aresetn" "m_src_axi_aresetn" \ -# "s_axis_valid" "s_axis_data" "s_axis_last" "m_axis_ready" \ -# "fifo_wr_en" "fifo_wr_din" "fifo_rd_en"} { -# set_property DRIVER_VALUE "0" [ipx::get_ports $port] -# } -# foreach port {"s_axis_user" "fifo_wr_sync"} { -# set_property DRIVER_VALUE "1" [ipx::get_ports $port] -# } -# ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -# set cc [ipx::current_core] -# foreach intf [ipx::get_bus_interfaces m_*_axi -of_objects $cc] { -# set para [ipx::add_bus_parameter SUPPORTS_NARROW_BURST $intf] -# set_property "VALUE" "0" $para -# } -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_list" "2 4 8 16 32" \ -# ] \ -# [ipx::get_user_parameters FIFO_SIZE -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "8" \ -# "value_validation_range_maximum" "32" \ -# ] \ -# [ipx::get_user_parameters DMA_LENGTH_WIDTH -of_objects $cc] -# foreach {k v} { \ -# "ASYNC_CLK_REQ_SRC" "true" \ -# "ASYNC_CLK_SRC_DEST" "true" \ -# "ASYNC_CLK_DEST_REQ" "true" \ -# "CYCLIC" "false" \ -# "DMA_2D_TRANSFER" "false" \ -# "SYNC_TRANSFER_START" "false" \ -# "AXI_SLICE_SRC" "false" \ -# "AXI_SLICE_DEST" "false" \ -# "DISABLE_DEBUG_REGISTERS" "false" \ -# "ENABLE_DIAGNOSTICS_IF" "false" \ -# } { \ -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" $v \ -# ] \ -# [ipx::get_user_parameters $k -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" $v \ -# ] \ -# [ipx::get_hdl_parameters $k -of_objects $cc] -# } -# set_property -dict [list \ -# "enablement_tcl_expr" "\$DMA_TYPE_SRC != 0" \ -# ] \ -# [ipx::get_user_parameters SYNC_TRANSFER_START -of_objects $cc] -# foreach dir {"SRC" "DEST"} { -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_list" "16 32 64 128 256 512 1024" \ -# ] \ -# [ipx::get_user_parameters DMA_DATA_WIDTH_${dir} -of_objects $cc] -# -# set_property -dict [list \ -# "value_validation_type" "pairs" \ -# "value_validation_pairs" {"AXI3" "1" "AXI4" "0"} \ -# "enablement_tcl_expr" "\$DMA_TYPE_${dir} == 0" \ -# ] \ -# [ipx::get_user_parameters DMA_AXI_PROTOCOL_${dir} -of_objects $cc] -# -# set_property -dict [list \ -# "value_validation_type" "pairs" \ -# "value_validation_pairs" { \ -# "Memory-Mapped AXI" "0" \ -# "Streaming AXI" "1" \ -# "FIFO Interface" "2" \ -# } \ -# ] \ -# [ipx::get_user_parameters DMA_TYPE_${dir} -of_objects $cc] -# } -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set g [ipgui::add_group -name {DMA Endpoint Configuration} -component $cc \ -# -parent $page0 -display_name {DMA Endpoint Configuration} \ -# -layout "horizontal"] -# set src_group [ipgui::add_group -name {Source} -component $cc -parent $g \ -# -display_name {Source}] -# set dest_group [ipgui::add_group -name {Destination} -component $cc -parent $g \ -# -display_name {Destination}] -# foreach {dir group} [list "SRC" $src_group "DEST" $dest_group] { -# set p [ipgui::get_guiparamspec -name "DMA_TYPE_${dir}" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "Type" \ -# ] $p -# -# set p [ipgui::get_guiparamspec -name "DMA_AXI_PROTOCOL_${dir}" -component $cc] -# ipgui::move_param -component $cc -order 1 $p -parent $group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "AXI Protocol" \ -# ] $p -# -# set p [ipgui::get_guiparamspec -name "DMA_DATA_WIDTH_${dir}" -component $cc] -# ipgui::move_param -component $cc -order 2 $p -parent $group -# set_property -dict [list \ -# "display_name" "Bus Width" \ -# ] $p -# -# set p [ipgui::get_guiparamspec -name "AXI_SLICE_${dir}" -component $cc] -# ipgui::move_param -component $cc -order 3 $p -parent $group -# set_property -dict [list \ -# "display_name" "Insert Register Slice" \ -# ] $p -# } -# set p [ipgui::get_guiparamspec -name "SYNC_TRANSFER_START" -component $cc] -# ipgui::move_param -component $cc -order 4 $p -parent $src_group -# set_property -dict [list \ -# "display_name" "Transfer Start Synchronization Support" \ -# ] $p -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration"] -# set p [ipgui::get_guiparamspec -name "ID" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $general_group -# set_property -dict [list \ -# "display_name" "Core ID" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "DMA_LENGTH_WIDTH" -component $cc] -# ipgui::move_param -component $cc -order 1 $p -parent $general_group -# set_property -dict [list \ -# "display_name" "DMA Transfer Length Register Width" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "FIFO_SIZE" -component $cc] -# ipgui::move_param -component $cc -order 2 $p -parent $general_group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "Store-and-Forward Memory Size (In Bursts)" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "MAX_BYTES_PER_BURST" -component $cc] -# ipgui::move_param -component $cc -order 3 $p -parent $general_group -# set_property -dict [list \ -# "display_name" "Maximum Bytes per Burst" \ -# ] $p -# set feature_group [ipgui::add_group -name "Features" -component $cc \ -# -parent $page0 -display_name "Features"] -# set p [ipgui::get_guiparamspec -name "CYCLIC" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $feature_group -# set_property -dict [list \ -# "display_name" "Cyclic Transfer Support" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "DMA_2D_TRANSFER" -component $cc] -# ipgui::move_param -component $cc -order 1 $p -parent $feature_group -# set_property -dict [list \ -# "display_name" "2D Transfer Support" \ -# ] $p -# set clk_group [ipgui::add_group -name {Clock Domain Configuration} -component $cc \ -# -parent $page0 -display_name {Clock Domain Configuration}] -# set p [ipgui::get_guiparamspec -name "ASYNC_CLK_REQ_SRC" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $clk_group -# set_property -dict [list \ -# "display_name" "Request and Source Clock Asynchronous" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "ASYNC_CLK_SRC_DEST" -component $cc] -# ipgui::move_param -component $cc -order 1 $p -parent $clk_group -# set_property -dict [list \ -# "display_name" "Source and Destination Clock Asynchronous" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "ASYNC_CLK_DEST_REQ" -component $cc] -# ipgui::move_param -component $cc -order 2 $p -parent $clk_group -# set_property -dict [list \ -# "display_name" "Destination and Request Clock Asynchronous" \ -# ] $p -# set dbg_group [ipgui::add_group -name {Debug} -component $cc \ -# -parent $page0 -display_name {Debug}] -# set p [ipgui::get_guiparamspec -name "DISABLE_DEBUG_REGISTERS" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $dbg_group -# set_property -dict [list \ -# "display_name" "Disable Debug Registers" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "ENABLE_DIAGNOSTICS_IF" -component $cc] -# ipgui::move_param -component $cc -order 1 $p -parent $dbg_group -# set_property -dict [list \ -# "display_name" "Enable Diagnostics Interface" \ -# ] $p -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXI_ADDR_WIDTH" -component $cc] -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_SRC" -component $cc] -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_DEST" -component $cc] -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "ALLOW_ASYM_MEM" -component $cc] -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXIS_ID_W" -component $cc] -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXIS_DEST_W" -component $cc] -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:23:00 2021... diff --git a/adi_library/axi_dmac/vivado.jou b/adi_library/axi_dmac/vivado.jou deleted file mode 100644 index d6bf2bea..00000000 --- a/adi_library/axi_dmac/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:22:35 2021 -# Process ID: 66563 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac -# Command line: vivado -mode batch -source axi_dmac_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac/vivado.jou -#----------------------------------------------------------- -source axi_dmac_ip.tcl diff --git a/adi_library/axi_dmac/vivado.log b/adi_library/axi_dmac/vivado.log deleted file mode 100644 index 3297cfeb..00000000 --- a/adi_library/axi_dmac/vivado.log +++ /dev/null @@ -1,1127 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:22:35 2021 -# Process ID: 66563 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac -# Command line: vivado -mode batch -source axi_dmac_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac/vivado.jou -#----------------------------------------------------------- -source axi_dmac_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_dmac -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_dmac [list \ -# "$ad_hdl_dir/library/common/ad_mem_asym.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "inc_id.vh" \ -# "resp.vh" \ -# "axi_dmac_burst_memory.v" \ -# "axi_dmac_regmap.v" \ -# "axi_dmac_regmap_request.v" \ -# "axi_dmac_reset_manager.v" \ -# "axi_dmac_resize_dest.v" \ -# "axi_dmac_resize_src.v" \ -# "axi_dmac_response_manager.v" \ -# "axi_dmac_transfer.v" \ -# "address_generator.v" \ -# "data_mover.v" \ -# "request_arb.v" \ -# "request_generator.v" \ -# "response_handler.v" \ -# "axi_register_slice.v" \ -# "2d_transfer.v" \ -# "dest_axi_mm.v" \ -# "dest_axi_stream.v" \ -# "dest_fifo_inf.v" \ -# "src_axi_mm.v" \ -# "src_axi_stream.v" \ -# "src_fifo_inf.v" \ -# "splitter.v" \ -# "response_generator.v" \ -# "axi_dmac.v" \ -# "axi_dmac_constr.ttcl" \ -# "axi_dmac_pkg_sv.ttcl" \ -# "bd/bd.tcl" ] -# adi_ip_properties axi_dmac -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac/axi_dmac_constr.ttcl' ignored by IP packager. -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac/axi_dmac_pkg_sv.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dest_request_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dest_data_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dest_address_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dest_response_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'src_request_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'src_data_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'src_address_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'src_response_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_req_measured_burst_length' has a dependency on the module local parameter or undefined parameter 'BYTES_PER_BURST_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_dma_req_dest_address' has a dependency on the module local parameter or undefined parameter 'BYTES_PER_BEAT_WIDTH_DEST'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_dma_req_src_address' has a dependency on the module local parameter or undefined parameter 'BYTES_PER_BEAT_WIDTH_SRC'. -INFO: [IP_Flow 19-1842] HDL Parser: Found include file "inc_id.vh" from the top-level HDL file. -INFO: [IP_Flow 19-1842] HDL Parser: Found include file "resp.vh" from the top-level HDL file. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_dest_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_src_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_dest_axi_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_src_axi_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'fifo_rd_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'fifo_wr_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'm_axis_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axis_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Synthesis'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Simulation'. -Resolution: Remove the file from the specified file group. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_infer_mm_interfaces axi_dmac -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'. -INFO: [IP_Flow 19-3164] Bus Interface 'm_dest_axi': References existing address space 'm_dest_axi'. -INFO: [IP_Flow 19-3164] Bus Interface 'm_src_axi': References existing address space 'm_src_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_dest_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_src_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_dest_axi_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_src_axi_aresetn'. -# adi_ip_ttcl axi_dmac "axi_dmac_constr.ttcl" -# adi_ip_sim_ttcl axi_dmac "axi_dmac_pkg_sv.ttcl" -# adi_ip_bd axi_dmac "bd/bd.tcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_axis_fifo:1.0 \ -# analog.com:user:util_cdc:1.0 \ -# } -# set_property display_name "ADI AXI DMA Controller" [ipx::current_core] -# set_property description "ADI AXI DMA Controller" [ipx::current_core] -# adi_add_bus "s_axis" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"s_axis_ready" "TREADY"} \ -# {"s_axis_valid" "TVALID"} \ -# {"s_axis_data" "TDATA"} \ -# {"s_axis_strb" "TSTRB"} \ -# {"s_axis_keep" "TKEEP"} \ -# {"s_axis_user" "TUSER"} \ -# {"s_axis_id" "TID"} \ -# {"s_axis_dest" "TDEST"} \ -# {"s_axis_last" "TLAST"}] -# adi_add_bus_clock "s_axis_aclk" "s_axis" -# adi_add_bus "m_axis" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"m_axis_ready" "TREADY"} \ -# {"m_axis_valid" "TVALID"} \ -# {"m_axis_data" "TDATA"} \ -# {"m_axis_strb" "TSTRB"} \ -# {"m_axis_keep" "TKEEP"} \ -# {"m_axis_user" "TUSER"} \ -# {"m_axis_id" "TID"} \ -# {"m_axis_dest" "TDEST"} \ -# {"m_axis_last" "TLAST"}] -# adi_add_bus_clock "m_axis_aclk" "m_axis" -# adi_set_bus_dependency "m_src_axi" "m_src_axi" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 0)" -# adi_set_bus_dependency "m_dest_axi" "m_dest_axi" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 0)" -# adi_set_bus_dependency "s_axis" "s_axis" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 1)" -# adi_set_bus_dependency "m_axis" "m_axis" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 1)" -# adi_set_ports_dependency "fifo_rd" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 2)" -# adi_set_ports_dependency "dest_diag_level_bursts" \ -# "(spirit:decode(id('MODELPARAM_VALUE.ENABLE_DIAGNOSTICS_IF')) = 1)" -# set dummy_axi_ports [list \ -# "m_dest_axi_arvalid" \ -# "m_dest_axi_arready" \ -# "m_dest_axi_araddr" \ -# "m_dest_axi_arlen" \ -# "m_dest_axi_arsize" \ -# "m_dest_axi_arburst" \ -# "m_dest_axi_arcache" \ -# "m_dest_axi_arprot" \ -# "m_dest_axi_rready" \ -# "m_dest_axi_rvalid" \ -# "m_dest_axi_rresp" \ -# "m_dest_axi_rdata" \ -# "m_src_axi_awvalid" \ -# "m_src_axi_awready" \ -# "m_src_axi_awvalid" \ -# "m_src_axi_awaddr" \ -# "m_src_axi_awlen" \ -# "m_src_axi_awsize" \ -# "m_src_axi_awburst" \ -# "m_src_axi_awcache" \ -# "m_src_axi_awprot" \ -# "m_src_axi_wvalid" \ -# "m_src_axi_wready" \ -# "m_src_axi_wvalid" \ -# "m_src_axi_wdata" \ -# "m_src_axi_wstrb" \ -# "m_src_axi_wlast" \ -# "m_src_axi_bready" \ -# "m_src_axi_bvalid" \ -# "m_src_axi_bresp" \ -# ] -# lappend dummy_axi_ports \ -# "m_dest_axi_awid" \ -# "m_dest_axi_awlock" \ -# "m_dest_axi_wid" \ -# "m_dest_axi_bid" \ -# "m_dest_axi_arid" \ -# "m_dest_axi_arlock" \ -# "m_dest_axi_rid" \ -# "m_dest_axi_rlast" \ -# "m_src_axi_arid" \ -# "m_src_axi_arlock" \ -# "m_src_axi_rid" \ -# "m_src_axi_awid" \ -# "m_src_axi_awlock" \ -# "m_src_axi_wid" \ -# "m_src_axi_bid" -# foreach p $dummy_axi_ports { -# adi_set_ports_dependency $p "false" -# } -# set_property master_address_space_ref m_dest_axi \ -# [ipx::get_bus_interfaces m_dest_axi \ -# -of_objects [ipx::current_core]] -# set_property master_address_space_ref m_src_axi \ -# [ipx::get_bus_interfaces m_src_axi \ -# -of_objects [ipx::current_core]] -# adi_add_bus "fifo_wr" "slave" \ -# "analog.com:interface:fifo_wr_rtl:1.0" \ -# "analog.com:interface:fifo_wr:1.0" \ -# { \ -# {"fifo_wr_en" "EN"} \ -# {"fifo_wr_din" "DATA"} \ -# {"fifo_wr_overflow" "OVERFLOW"} \ -# {"fifo_wr_sync" "SYNC"} \ -# {"fifo_wr_xfer_req" "XFER_REQ"} \ -# } -# adi_add_bus_clock "fifo_wr_clk" "fifo_wr" -# adi_set_bus_dependency "fifo_wr" "fifo_wr" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 2)" -# adi_add_bus "fifo_rd" "slave" \ -# "analog.com:interface:fifo_rd_rtl:1.0" \ -# "analog.com:interface:fifo_rd:1.0" \ -# { -# {"fifo_rd_en" "EN"} \ -# {"fifo_rd_dout" "DATA"} \ -# {"fifo_rd_valid" "VALID"} \ -# {"fifo_rd_underflow" "UNDERFLOW"} \ -# } -# adi_add_bus_clock "fifo_rd_clk" "fifo_rd" -# adi_set_bus_dependency "fifo_rd" "fifo_rd" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 2)" -# foreach port {"m_dest_axi_aresetn" "m_src_axi_aresetn" \ -# "s_axis_valid" "s_axis_data" "s_axis_last" "m_axis_ready" \ -# "fifo_wr_en" "fifo_wr_din" "fifo_rd_en"} { -# set_property DRIVER_VALUE "0" [ipx::get_ports $port] -# } -# foreach port {"s_axis_user" "fifo_wr_sync"} { -# set_property DRIVER_VALUE "1" [ipx::get_ports $port] -# } -# ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -# set cc [ipx::current_core] -# foreach intf [ipx::get_bus_interfaces m_*_axi -of_objects $cc] { -# set para [ipx::add_bus_parameter SUPPORTS_NARROW_BURST $intf] -# set_property "VALUE" "0" $para -# } -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_list" "2 4 8 16 32" \ -# ] \ -# [ipx::get_user_parameters FIFO_SIZE -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "8" \ -# "value_validation_range_maximum" "32" \ -# ] \ -# [ipx::get_user_parameters DMA_LENGTH_WIDTH -of_objects $cc] -# foreach {k v} { \ -# "ASYNC_CLK_REQ_SRC" "true" \ -# "ASYNC_CLK_SRC_DEST" "true" \ -# "ASYNC_CLK_DEST_REQ" "true" \ -# "CYCLIC" "false" \ -# "DMA_2D_TRANSFER" "false" \ -# "SYNC_TRANSFER_START" "false" \ -# "AXI_SLICE_SRC" "false" \ -# "AXI_SLICE_DEST" "false" \ -# "DISABLE_DEBUG_REGISTERS" "false" \ -# "ENABLE_DIAGNOSTICS_IF" "false" \ -# } { \ -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" $v \ -# ] \ -# [ipx::get_user_parameters $k -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" $v \ -# ] \ -# [ipx::get_hdl_parameters $k -of_objects $cc] -# } -# set_property -dict [list \ -# "enablement_tcl_expr" "\$DMA_TYPE_SRC != 0" \ -# ] \ -# [ipx::get_user_parameters SYNC_TRANSFER_START -of_objects $cc] -# foreach dir {"SRC" "DEST"} { -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_list" "16 32 64 128 256 512 1024" \ -# ] \ -# [ipx::get_user_parameters DMA_DATA_WIDTH_${dir} -of_objects $cc] -# -# set_property -dict [list \ -# "value_validation_type" "pairs" \ -# "value_validation_pairs" {"AXI3" "1" "AXI4" "0"} \ -# "enablement_tcl_expr" "\$DMA_TYPE_${dir} == 0" \ -# ] \ -# [ipx::get_user_parameters DMA_AXI_PROTOCOL_${dir} -of_objects $cc] -# -# set_property -dict [list \ -# "value_validation_type" "pairs" \ -# "value_validation_pairs" { \ -# "Memory-Mapped AXI" "0" \ -# "Streaming AXI" "1" \ -# "FIFO Interface" "2" \ -# } \ -# ] \ -# [ipx::get_user_parameters DMA_TYPE_${dir} -of_objects $cc] -# } -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set g [ipgui::add_group -name {DMA Endpoint Configuration} -component $cc \ -# -parent $page0 -display_name {DMA Endpoint Configuration} \ -# -layout "horizontal"] -# set src_group [ipgui::add_group -name {Source} -component $cc -parent $g \ -# -display_name {Source}] -# set dest_group [ipgui::add_group -name {Destination} -component $cc -parent $g \ -# -display_name {Destination}] -# foreach {dir group} [list "SRC" $src_group "DEST" $dest_group] { -# set p [ipgui::get_guiparamspec -name "DMA_TYPE_${dir}" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "Type" \ -# ] $p -# -# set p [ipgui::get_guiparamspec -name "DMA_AXI_PROTOCOL_${dir}" -component $cc] -# ipgui::move_param -component $cc -order 1 $p -parent $group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "AXI Protocol" \ -# ] $p -# -# set p [ipgui::get_guiparamspec -name "DMA_DATA_WIDTH_${dir}" -component $cc] -# ipgui::move_param -component $cc -order 2 $p -parent $group -# set_property -dict [list \ -# "display_name" "Bus Width" \ -# ] $p -# -# set p [ipgui::get_guiparamspec -name "AXI_SLICE_${dir}" -component $cc] -# ipgui::move_param -component $cc -order 3 $p -parent $group -# set_property -dict [list \ -# "display_name" "Insert Register Slice" \ -# ] $p -# } -# set p [ipgui::get_guiparamspec -name "SYNC_TRANSFER_START" -component $cc] -# ipgui::move_param -component $cc -order 4 $p -parent $src_group -# set_property -dict [list \ -# "display_name" "Transfer Start Synchronization Support" \ -# ] $p -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration"] -# set p [ipgui::get_guiparamspec -name "ID" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $general_group -# set_property -dict [list \ -# "display_name" "Core ID" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "DMA_LENGTH_WIDTH" -component $cc] -# ipgui::move_param -component $cc -order 1 $p -parent $general_group -# set_property -dict [list \ -# "display_name" "DMA Transfer Length Register Width" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "FIFO_SIZE" -component $cc] -# ipgui::move_param -component $cc -order 2 $p -parent $general_group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "Store-and-Forward Memory Size (In Bursts)" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "MAX_BYTES_PER_BURST" -component $cc] -# ipgui::move_param -component $cc -order 3 $p -parent $general_group -# set_property -dict [list \ -# "display_name" "Maximum Bytes per Burst" \ -# ] $p -# set feature_group [ipgui::add_group -name "Features" -component $cc \ -# -parent $page0 -display_name "Features"] -# set p [ipgui::get_guiparamspec -name "CYCLIC" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $feature_group -# set_property -dict [list \ -# "display_name" "Cyclic Transfer Support" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "DMA_2D_TRANSFER" -component $cc] -# ipgui::move_param -component $cc -order 1 $p -parent $feature_group -# set_property -dict [list \ -# "display_name" "2D Transfer Support" \ -# ] $p -# set clk_group [ipgui::add_group -name {Clock Domain Configuration} -component $cc \ -# -parent $page0 -display_name {Clock Domain Configuration}] -# set p [ipgui::get_guiparamspec -name "ASYNC_CLK_REQ_SRC" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $clk_group -# set_property -dict [list \ -# "display_name" "Request and Source Clock Asynchronous" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "ASYNC_CLK_SRC_DEST" -component $cc] -# ipgui::move_param -component $cc -order 1 $p -parent $clk_group -# set_property -dict [list \ -# "display_name" "Source and Destination Clock Asynchronous" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "ASYNC_CLK_DEST_REQ" -component $cc] -# ipgui::move_param -component $cc -order 2 $p -parent $clk_group -# set_property -dict [list \ -# "display_name" "Destination and Request Clock Asynchronous" \ -# ] $p -# set dbg_group [ipgui::add_group -name {Debug} -component $cc \ -# -parent $page0 -display_name {Debug}] -# set p [ipgui::get_guiparamspec -name "DISABLE_DEBUG_REGISTERS" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $dbg_group -# set_property -dict [list \ -# "display_name" "Disable Debug Registers" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "ENABLE_DIAGNOSTICS_IF" -component $cc] -# ipgui::move_param -component $cc -order 1 $p -parent $dbg_group -# set_property -dict [list \ -# "display_name" "Enable Diagnostics Interface" \ -# ] $p -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXI_ADDR_WIDTH" -component $cc] -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_SRC" -component $cc] -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_DEST" -component $cc] -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "ALLOW_ASYM_MEM" -component $cc] -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXIS_ID_W" -component $cc] -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXIS_DEST_W" -component $cc] -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:23:00 2021... diff --git a/adi_library/axi_fan_control/axi_fan_control_ip.log b/adi_library/axi_fan_control/axi_fan_control_ip.log deleted file mode 100644 index 5d8f1eb5..00000000 --- a/adi_library/axi_fan_control/axi_fan_control_ip.log +++ /dev/null @@ -1,1005 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_fan_control_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_fan_control -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_fan_control [list \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/util_pulse_gen.v" \ -# "axi_fan_control.v"] -# adi_ip_properties axi_fan_control -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'state' has a dependency on the module local parameter or undefined parameter 'INIT'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_00_h' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_000'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_25_l' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_025_L'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_25_h' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_025_H'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_50_l' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_050_L'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_50_h' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_050_H'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_75_l' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_075_L'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_75_h' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_075_H'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_100_l' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_100'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# set cc [ipx::current_core] -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:14:22 2021... diff --git a/adi_library/axi_fan_control/vivado.jou b/adi_library/axi_fan_control/vivado.jou deleted file mode 100644 index c38ca349..00000000 --- a/adi_library/axi_fan_control/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:14:14 2021 -# Process ID: 5439 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control -# Command line: vivado -mode batch -source axi_fan_control_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control/vivado.jou -#----------------------------------------------------------- -source axi_fan_control_ip.tcl diff --git a/adi_library/axi_fan_control/vivado.log b/adi_library/axi_fan_control/vivado.log deleted file mode 100644 index 936ec883..00000000 --- a/adi_library/axi_fan_control/vivado.log +++ /dev/null @@ -1,1010 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:14:14 2021 -# Process ID: 5439 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control -# Command line: vivado -mode batch -source axi_fan_control_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control/vivado.jou -#----------------------------------------------------------- -source axi_fan_control_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_fan_control -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_fan_control [list \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/util_pulse_gen.v" \ -# "axi_fan_control.v"] -# adi_ip_properties axi_fan_control -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fan_control'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'state' has a dependency on the module local parameter or undefined parameter 'INIT'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_00_h' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_000'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_25_l' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_025_L'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_25_h' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_025_H'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_50_l' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_050_L'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_50_h' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_050_H'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_75_l' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_075_L'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_75_h' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_075_H'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_temp_100_l' has a dependency on the module local parameter or undefined parameter 'THRESH_PWM_100'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# set cc [ipx::current_core] -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:14:22 2021... diff --git a/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.log b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.log deleted file mode 100644 index d6859d1e..00000000 --- a/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.log +++ /dev/null @@ -1,3827 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_fmcadc5_sync_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_fmcadc5_sync -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_fmcadc5_sync [list \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_out.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "axi_fmcadc5_sync_constr.xdc" \ -# "axi_fmcadc5_sync_calcor.v" \ -# "axi_fmcadc5_sync.v" ] -# adi_ip_properties axi_fmcadc5_sync -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '511:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_n' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_p' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_100' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_101' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_102' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_103' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_104' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_105' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_106' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_107' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_108' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_109' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_110' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_111' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_112' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_113' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_114' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_115' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_116' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_117' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_118' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_119' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_120' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_121' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_122' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_123' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_124' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_125' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_126' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_127' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_128' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_129' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_130' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_131' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_132' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_133' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_134' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_135' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_136' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_137' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_138' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_139' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_140' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_141' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_142' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_143' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_144' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_145' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_146' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_147' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_148' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_149' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_150' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_151' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_152' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_153' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_154' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_155' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_156' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_157' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_158' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_159' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_160' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_161' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_162' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_163' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_164' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_165' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_166' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_167' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_168' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_169' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_170' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_171' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_172' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_173' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_174' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_175' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_176' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_177' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_178' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_179' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_180' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_181' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_182' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_183' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_184' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_185' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_186' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '511:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '511:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '511:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'delay_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'delay_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_sync_0_n' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_n': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_n': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_sync_0_p' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_p': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_p': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_128': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_129': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_130': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_131': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_132': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_133': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_134': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_135': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_136': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_137': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_138': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_139': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_140': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_141': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_142': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_143': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_144': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_145': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_146': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_147': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_148': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_149': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_150': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_151': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_152': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_153': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_154': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_155': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_156': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_157': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_158': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_159': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_160': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_161': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_162': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_163': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_164': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_165': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_166': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_167': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_168': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_169': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_170': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_171': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_172': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_173': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_174': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_175': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_176': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_177': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_178': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_179': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_180': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_181': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_182': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_183': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_184': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_185': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_186': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_187': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_188': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_189': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_190': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_191': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_192': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_193': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_194': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_195': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_196': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_197': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_198': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_199': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_sync_1_n' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_n': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_n': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_sync_1_p' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_p': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_p': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_200': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_201': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_202': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_203': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_204': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_205': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_206': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_207': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_208': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_209': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_210': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_211': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_212': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_213': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_214': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_215': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_216': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_217': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_218': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_219': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_220': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_221': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_222': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_223': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_224': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_225': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_226': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_227': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_228': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_229': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_230': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_231': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_232': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_233': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_234': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_235': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_236': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_237': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_238': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_239': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_240': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_241': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_242': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_243': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_244': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_245': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_246': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_247': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_248': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_249': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_250': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_251': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_252': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_253': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_254': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_255': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_256': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_257': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_258': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_259': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_260': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_261': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_262': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_263': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_264': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_265': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_266': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_267': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_268': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_269': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_270': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_271': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_272': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_273': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_274': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_275': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_276': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_277': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_278': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_279': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_280': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_281': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_282': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_283': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_284': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_285': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_286': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_287': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_288': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_289': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_290': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_291': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_292': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_293': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_294': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_295': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_296': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_297': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_298': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_299': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_300': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_301': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_302': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_303': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_304': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_305': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_306': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_307': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_308': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_309': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_310': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_311': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_312': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_313': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_314': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_315': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_316': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_317': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_318': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_319': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_320': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_321': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_322': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_323': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_324': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_325': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_326': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_327': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_328': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_329': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_330': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_331': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_332': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_333': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_334': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_335': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_336': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_337': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_338': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_339': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_340': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_341': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_342': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_343': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_344': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_345': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_346': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_347': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_348': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_349': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_350': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_351': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_352': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_353': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_354': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_355': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_356': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_357': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_358': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_359': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_360': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_361': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_362': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_363': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_364': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_365': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_366': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_367': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_368': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_369': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_370': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_371': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_372': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_373': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_374': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_375': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_376': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_377': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_378': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_379': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_380': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_381': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_382': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_383': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_384': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_385': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_386': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_387': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_388': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_389': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_390': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_391': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_392': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_393': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_394': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_395': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_396': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_397': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_398': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_399': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_400': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_401': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_402': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_403': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_404': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_405': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_406': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_407': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_408': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_409': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_410': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_411': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_412': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_413': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_414': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_415': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_416': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_417': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_418': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_419': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_420': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_421': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_422': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_423': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_424': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_425': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_426': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_427': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_428': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_429': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_430': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_431': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_432': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_433': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_434': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_435': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_436': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_437': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_438': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_439': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_440': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_441': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_442': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_443': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_444': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_445': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_446': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_447': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_448': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_449': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_450': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_451': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_452': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_453': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_454': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_455': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_456': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_457': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_458': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_459': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_460': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_461': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_462': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_463': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_464': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_465': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_466': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_467': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_468': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_469': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_470': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_471': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_472': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_473': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_474': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_475': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_476': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_477': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_478': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_479': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_480': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_481': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_482': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_483': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_484': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_485': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_486': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_487': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_488': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_489': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_490': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_491': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_492': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_493': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_494': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_495': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_496': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_497': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_498': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_499': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_500': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_501': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_502': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_503': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_504': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_505': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_506': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_507': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_508': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_509': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_510': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_511': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_0': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_1': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_10': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_100': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_101': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_102': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_103': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_104': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_105': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_106': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_107': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_108': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_109': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_11': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_110': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_111': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_112': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_113': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_114': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_115': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_116': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_117': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_118': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_119': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_12': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_120': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_121': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_122': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_123': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_124': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_125': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_126': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_127': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_128': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_128': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_129': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_129': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_13': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_130': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_130': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_131': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_131': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_132': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_132': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_133': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_133': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_134': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_134': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_135': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_135': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_136': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_136': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_137': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_137': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_138': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_138': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_139': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_139': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_14': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_140': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_140': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_141': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_141': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_142': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_142': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_143': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_143': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_144': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_144': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_145': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_145': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_146': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_146': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_147': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_147': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_148': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_148': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_149': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_149': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_15': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_150': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_150': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_151': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_151': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_152': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_152': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_153': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_153': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_154': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_154': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_155': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_155': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_156': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_156': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_157': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_157': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_158': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_158': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_159': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_159': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_16': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_160': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_160': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_161': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_161': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_162': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_162': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_163': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_163': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_164': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_164': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_165': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_165': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_166': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_166': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_167': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_167': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_168': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_168': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_169': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_169': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_17': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_170': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_170': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_171': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_171': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_172': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_172': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_173': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_173': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_174': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_174': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_175': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_175': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_176': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_176': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_177': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_177': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_178': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_178': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_179': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_179': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_18': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_180': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_180': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_181': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_181': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_182': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_182': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_183': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_183': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_184': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_184': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_185': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_185': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_186': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_186': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_187': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_187': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_188': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_188': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_189': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_189': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_19': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_190': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_190': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_191': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_191': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_192': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_192': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_193': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_193': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_194': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_194': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_195': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_195': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_196': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_196': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_197': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_197': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_198': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_198': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_199': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_199': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_2': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_20': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_200': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_200': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_201': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_201': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_202': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_202': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_203': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_203': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_204': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_204': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_205': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_205': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_206': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_206': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_207': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_207': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_208': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_208': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_209': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_209': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_21': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_210': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_210': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_211': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_211': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_212': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_212': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_213': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_213': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_214': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_214': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_215': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_215': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_216': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_216': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_217': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_217': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_218': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_218': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_219': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_219': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_22': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_220': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_220': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_221': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_221': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_222': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_222': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_223': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_223': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_224': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_224': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_225': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_225': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_226': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_226': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_227': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_227': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_228': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_228': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_229': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_229': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_23': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_230': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_230': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_231': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_231': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_232': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_232': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_233': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_233': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_234': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_234': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_235': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_235': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_236': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_236': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_237': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_237': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_238': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_238': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_239': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_239': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_24': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_240': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_240': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_241': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_241': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_242': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_242': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_243': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_243': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_244': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_244': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_245': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_245': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_246': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_246': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_247': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_247': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_248': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_248': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_249': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_249': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_25': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_250': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_250': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_251': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_251': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_252': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_252': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_253': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_253': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_254': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_254': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_255': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_255': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_26': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_27': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_28': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_29': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_3': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_30': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_31': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_32': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_33': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_34': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_35': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_36': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_37': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_38': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_39': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_4': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_40': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_41': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_42': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_43': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_44': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_45': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_46': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_47': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_48': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_49': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_5': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_50': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_51': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_52': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_53': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_54': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_55': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_56': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_57': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_58': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_59': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_6': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_60': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_61': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_62': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_63': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_64': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_65': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_66': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_67': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_68': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_69': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_7': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_70': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_71': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_72': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_73': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_74': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_75': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_76': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_77': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_78': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_79': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_8': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_80': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_81': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_82': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_83': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_84': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_85': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_86': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_87': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_88': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_89': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_9': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_90': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_91': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_92': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_93': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_94': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_95': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_96': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_97': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_98': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_99': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_0': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_1': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_10': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_100': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_101': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_102': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_103': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_104': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_105': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_106': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_107': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_108': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_109': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_11': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_110': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_111': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_112': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_113': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_114': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_115': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_116': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_117': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_118': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_119': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_12': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_120': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_121': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_122': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_123': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_124': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_125': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_126': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_127': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_128': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_128': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_129': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_129': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_13': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_130': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_130': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_131': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_131': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_132': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_132': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_133': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_133': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_134': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_134': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_135': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_135': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_136': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_136': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_137': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_137': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_138': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_138': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_139': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_139': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_14': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_140': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_140': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_141': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_141': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_142': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_142': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_143': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_143': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_144': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_144': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_145': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_145': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_146': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_146': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_147': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_147': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_148': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_148': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_149': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_149': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_15': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_150': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_150': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_151': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_151': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_152': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_152': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_153': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_153': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_154': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_154': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_155': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_155': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_156': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_156': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_157': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_157': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_158': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_158': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_159': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_159': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_16': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_160': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_160': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_161': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_161': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_162': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_162': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_163': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_163': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_164': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_164': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_165': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_165': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_166': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_166': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_167': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_167': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_168': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_168': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_169': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_169': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_17': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_170': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_170': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_171': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_171': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_172': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_172': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_173': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_173': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_174': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_174': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_175': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_175': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_176': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_176': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_177': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_177': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_178': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_178': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_179': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_179': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_18': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_180': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_180': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_181': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_181': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_182': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_182': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_183': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_183': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_184': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_184': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_185': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_185': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_186': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_186': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_187': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_187': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_188': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_188': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_189': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_189': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_19': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_190': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_190': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_191': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_191': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_192': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_192': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_193': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_193': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_194': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_194': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_195': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_195': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_196': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_196': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_197': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_197': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_198': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_198': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_199': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_199': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_2': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_20': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_200': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_200': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_201': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_201': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_202': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_202': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_203': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_203': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_204': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_204': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_205': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_205': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_206': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_206': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_207': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_207': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_208': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_208': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_209': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_209': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_21': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_210': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_210': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_211': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_211': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_212': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_212': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_213': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_213': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_214': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_214': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_215': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_215': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_216': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_216': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_217': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_217': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_218': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_218': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_219': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_219': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_22': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_220': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_220': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_221': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_221': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_222': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_222': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_223': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_223': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_224': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_224': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_225': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_225': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_226': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_226': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_227': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_227': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_228': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_228': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_229': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_229': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_23': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_230': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_230': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_231': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_231': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_232': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_232': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_233': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_233': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_234': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_234': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_235': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_235': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_236': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_236': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_237': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_237': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_238': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_238': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_239': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_239': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_24': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_240': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_240': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_241': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_241': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_242': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_242': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_243': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_243': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_244': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_244': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_245': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_245': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_246': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_246': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_247': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_247': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_248': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_248': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_249': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_249': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_25': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_250': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_250': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_251': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_251': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_252': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_252': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_253': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_253': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_254': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_254': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_255': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_255': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_26': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_27': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_28': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_29': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_3': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_30': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_31': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_32': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_33': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_34': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_35': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_36': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_37': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_38': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_39': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_4': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_40': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_41': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_42': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_43': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_44': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_45': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_46': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_47': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_48': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_49': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_5': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_50': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_51': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_52': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_53': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_54': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_55': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_56': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_57': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_58': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_59': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_6': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_60': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_61': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_62': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_63': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_64': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_65': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_66': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_67': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_68': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_69': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_7': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_70': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_71': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_72': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_73': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_74': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_75': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_76': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_77': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_78': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_79': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_8': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_80': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_81': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_82': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_83': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_84': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_85': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_86': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_87': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_88': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_89': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_9': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_90': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_91': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_92': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_93': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_94': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_95': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_96': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_97': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_98': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_99': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'spi_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'spi_clk': FREQ_HZ bus parameter is missing for output clock interface. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_fmcadc5_sync "bd/bd.tcl" -# ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface delay_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'delay_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'delay_rst'. -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:14:33 2021... diff --git a/adi_library/axi_fmcadc5_sync/vivado.jou b/adi_library/axi_fmcadc5_sync/vivado.jou deleted file mode 100644 index d8080996..00000000 --- a/adi_library/axi_fmcadc5_sync/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:14:22 2021 -# Process ID: 5495 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync -# Command line: vivado -mode batch -source axi_fmcadc5_sync_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync/vivado.jou -#----------------------------------------------------------- -source axi_fmcadc5_sync_ip.tcl diff --git a/adi_library/axi_fmcadc5_sync/vivado.log b/adi_library/axi_fmcadc5_sync/vivado.log deleted file mode 100644 index 496a0857..00000000 --- a/adi_library/axi_fmcadc5_sync/vivado.log +++ /dev/null @@ -1,3832 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:14:22 2021 -# Process ID: 5495 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync -# Command line: vivado -mode batch -source axi_fmcadc5_sync_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync/vivado.jou -#----------------------------------------------------------- -source axi_fmcadc5_sync_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_fmcadc5_sync -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_fmcadc5_sync [list \ -# "$ad_hdl_dir/library/xilinx/common/ad_data_out.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "axi_fmcadc5_sync_constr.xdc" \ -# "axi_fmcadc5_sync_calcor.v" \ -# "axi_fmcadc5_sync.v" ] -# adi_ip_properties axi_fmcadc5_sync -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_data_out.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_fmcadc5_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '511:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_n' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_p' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_100' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_101' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_102' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_103' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_104' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_105' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_106' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_107' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_108' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_109' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_110' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_111' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_112' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_113' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_114' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_115' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_116' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_117' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_118' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_119' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_120' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_121' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_122' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_123' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_124' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_125' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_126' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_127' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_128' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_129' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_130' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_131' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_132' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_133' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_134' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_135' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_136' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_137' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_138' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_139' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_140' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_141' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_142' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_143' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_144' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_145' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_146' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_147' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_148' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_149' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_150' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_151' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_152' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_153' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_154' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_155' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_156' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_157' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_158' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_159' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_160' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_161' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_162' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_163' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_164' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_165' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_166' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_167' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_168' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_169' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_170' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_171' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_172' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_173' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_174' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_175' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_176' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_177' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_178' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_179' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_180' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_181' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_182' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_183' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_184' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_185' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_186' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '511:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '511:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '511:0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '255:0' is present in all ports of the interface 'rx_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'delay_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'delay_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_sync_0_n' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_n': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_n': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_sync_0_p' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_p': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_p': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_128': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_129': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_130': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_131': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_132': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_133': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_134': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_135': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_136': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_137': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_138': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_139': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_140': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_141': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_142': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_143': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_144': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_145': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_146': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_147': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_148': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_149': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_150': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_151': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_152': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_153': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_154': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_155': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_156': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_157': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_158': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_159': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_160': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_161': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_162': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_163': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_164': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_165': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_166': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_167': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_168': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_169': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_170': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_171': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_172': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_173': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_174': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_175': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_176': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_177': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_178': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_179': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_180': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_181': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_182': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_183': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_184': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_185': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_186': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_187': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_188': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_189': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_190': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_191': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_192': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_193': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_194': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_195': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_196': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_197': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_198': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_199': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_sync_1_n' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_n': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_n': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_sync_1_p' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_p': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_p': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_200': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_201': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_202': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_203': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_204': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_205': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_206': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_207': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_208': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_209': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_210': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_211': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_212': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_213': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_214': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_215': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_216': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_217': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_218': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_219': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_220': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_221': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_222': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_223': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_224': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_225': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_226': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_227': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_228': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_229': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_230': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_231': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_232': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_233': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_234': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_235': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_236': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_237': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_238': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_239': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_240': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_241': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_242': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_243': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_244': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_245': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_246': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_247': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_248': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_249': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_250': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_251': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_252': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_253': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_254': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_255': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_256': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_257': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_258': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_259': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_260': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_261': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_262': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_263': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_264': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_265': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_266': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_267': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_268': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_269': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_270': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_271': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_272': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_273': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_274': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_275': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_276': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_277': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_278': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_279': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_280': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_281': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_282': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_283': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_284': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_285': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_286': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_287': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_288': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_289': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_290': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_291': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_292': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_293': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_294': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_295': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_296': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_297': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_298': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_299': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_300': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_301': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_302': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_303': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_304': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_305': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_306': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_307': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_308': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_309': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_310': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_311': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_312': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_313': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_314': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_315': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_316': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_317': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_318': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_319': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_320': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_321': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_322': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_323': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_324': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_325': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_326': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_327': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_328': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_329': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_330': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_331': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_332': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_333': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_334': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_335': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_336': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_337': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_338': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_339': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_340': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_341': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_342': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_343': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_344': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_345': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_346': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_347': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_348': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_349': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_350': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_351': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_352': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_353': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_354': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_355': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_356': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_357': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_358': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_359': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_360': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_361': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_362': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_363': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_364': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_365': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_366': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_367': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_368': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_369': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_370': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_371': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_372': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_373': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_374': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_375': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_376': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_377': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_378': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_379': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_380': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_381': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_382': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_383': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_384': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_385': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_386': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_387': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_388': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_389': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_390': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_391': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_392': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_393': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_394': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_395': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_396': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_397': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_398': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_399': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_400': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_401': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_402': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_403': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_404': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_405': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_406': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_407': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_408': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_409': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_410': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_411': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_412': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_413': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_414': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_415': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_416': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_417': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_418': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_419': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_420': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_421': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_422': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_423': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_424': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_425': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_426': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_427': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_428': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_429': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_430': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_431': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_432': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_433': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_434': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_435': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_436': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_437': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_438': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_439': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_440': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_441': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_442': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_443': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_444': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_445': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_446': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_447': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_448': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_449': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_450': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_451': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_452': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_453': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_454': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_455': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_456': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_457': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_458': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_459': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_460': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_461': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_462': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_463': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_464': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_465': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_466': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_467': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_468': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_469': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_470': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_471': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_472': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_473': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_474': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_475': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_476': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_477': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_478': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_479': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_480': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_481': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_482': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_483': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_484': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_485': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_486': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_487': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_488': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_489': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_490': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_491': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_492': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_493': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_494': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_495': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_496': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_497': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_498': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_499': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_500': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_501': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_502': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_503': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_504': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_505': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_506': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_507': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_508': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_509': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_510': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_511': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_0': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_1': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_10': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_100': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_101': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_102': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_103': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_104': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_105': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_106': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_107': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_108': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_109': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_11': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_110': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_111': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_112': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_113': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_114': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_115': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_116': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_117': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_118': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_119': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_12': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_120': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_121': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_122': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_123': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_124': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_125': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_126': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_127': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_128': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_128': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_129': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_129': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_13': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_130': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_130': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_131': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_131': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_132': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_132': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_133': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_133': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_134': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_134': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_135': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_135': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_136': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_136': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_137': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_137': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_138': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_138': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_139': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_139': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_14': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_140': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_140': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_141': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_141': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_142': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_142': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_143': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_143': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_144': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_144': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_145': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_145': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_146': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_146': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_147': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_147': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_148': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_148': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_149': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_149': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_15': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_150': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_150': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_151': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_151': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_152': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_152': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_153': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_153': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_154': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_154': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_155': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_155': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_156': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_156': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_157': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_157': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_158': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_158': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_159': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_159': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_16': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_160': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_160': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_161': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_161': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_162': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_162': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_163': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_163': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_164': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_164': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_165': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_165': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_166': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_166': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_167': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_167': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_168': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_168': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_169': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_169': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_17': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_170': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_170': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_171': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_171': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_172': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_172': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_173': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_173': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_174': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_174': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_175': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_175': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_176': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_176': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_177': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_177': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_178': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_178': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_179': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_179': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_18': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_180': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_180': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_181': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_181': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_182': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_182': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_183': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_183': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_184': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_184': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_185': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_185': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_186': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_186': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_187': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_187': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_188': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_188': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_189': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_189': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_19': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_190': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_190': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_191': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_191': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_192': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_192': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_193': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_193': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_194': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_194': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_195': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_195': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_196': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_196': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_197': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_197': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_198': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_198': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_199': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_199': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_2': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_20': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_200': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_200': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_201': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_201': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_202': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_202': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_203': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_203': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_204': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_204': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_205': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_205': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_206': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_206': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_207': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_207': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_208': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_208': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_209': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_209': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_21': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_210': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_210': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_211': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_211': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_212': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_212': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_213': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_213': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_214': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_214': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_215': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_215': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_216': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_216': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_217': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_217': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_218': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_218': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_219': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_219': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_22': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_220': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_220': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_221': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_221': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_222': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_222': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_223': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_223': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_224': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_224': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_225': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_225': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_226': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_226': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_227': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_227': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_228': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_228': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_229': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_229': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_23': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_230': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_230': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_231': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_231': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_232': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_232': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_233': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_233': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_234': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_234': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_235': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_235': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_236': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_236': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_237': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_237': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_238': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_238': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_239': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_239': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_24': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_240': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_240': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_241': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_241': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_242': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_242': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_243': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_243': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_244': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_244': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_245': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_245': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_246': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_246': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_247': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_247': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_248': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_248': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_249': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_249': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_25': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_250': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_250': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_251': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_251': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_252': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_252': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_253': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_253': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_254': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_254': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_255': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_255': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_26': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_27': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_28': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_29': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_3': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_30': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_31': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_32': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_33': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_34': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_35': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_36': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_37': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_38': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_39': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_4': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_40': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_41': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_42': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_43': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_44': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_45': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_46': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_47': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_48': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_49': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_5': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_50': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_51': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_52': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_53': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_54': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_55': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_56': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_57': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_58': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_59': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_6': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_60': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_61': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_62': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_63': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_64': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_65': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_66': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_67': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_68': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_69': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_7': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_70': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_71': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_72': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_73': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_74': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_75': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_76': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_77': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_78': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_79': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_8': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_80': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_81': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_82': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_83': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_84': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_85': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_86': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_87': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_88': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_89': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_9': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_90': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_91': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_92': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_93': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_94': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_95': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_96': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_97': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_98': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_99': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_0': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_1': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_10': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_100': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_100': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_101': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_101': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_102': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_102': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_103': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_103': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_104': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_104': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_105': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_105': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_106': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_106': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_107': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_107': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_108': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_108': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_109': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_109': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_11': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_110': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_110': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_111': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_111': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_112': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_112': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_113': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_113': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_114': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_114': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_115': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_115': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_116': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_116': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_117': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_117': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_118': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_118': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_119': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_119': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_12': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_120': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_120': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_121': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_121': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_122': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_122': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_123': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_123': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_124': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_124': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_125': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_125': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_126': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_126': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_127': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_127': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_128': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_128': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_129': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_129': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_13': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_130': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_130': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_131': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_131': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_132': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_132': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_133': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_133': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_134': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_134': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_135': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_135': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_136': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_136': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_137': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_137': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_138': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_138': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_139': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_139': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_14': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_140': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_140': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_141': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_141': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_142': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_142': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_143': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_143': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_144': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_144': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_145': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_145': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_146': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_146': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_147': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_147': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_148': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_148': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_149': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_149': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_15': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_150': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_150': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_151': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_151': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_152': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_152': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_153': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_153': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_154': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_154': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_155': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_155': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_156': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_156': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_157': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_157': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_158': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_158': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_159': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_159': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_16': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_160': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_160': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_161': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_161': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_162': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_162': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_163': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_163': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_164': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_164': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_165': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_165': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_166': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_166': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_167': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_167': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_168': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_168': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_169': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_169': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_17': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_170': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_170': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_171': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_171': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_172': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_172': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_173': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_173': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_174': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_174': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_175': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_175': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_176': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_176': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_177': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_177': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_178': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_178': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_179': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_179': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_18': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_180': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_180': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_181': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_181': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_182': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_182': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_183': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_183': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_184': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_184': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_185': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_185': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_186': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_186': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_187': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_187': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_188': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_188': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_189': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_189': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_19': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_190': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_190': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_191': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_191': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_192': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_192': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_193': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_193': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_194': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_194': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_195': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_195': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_196': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_196': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_197': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_197': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_198': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_198': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_199': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_199': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_2': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_20': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_200': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_200': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_201': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_201': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_202': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_202': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_203': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_203': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_204': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_204': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_205': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_205': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_206': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_206': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_207': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_207': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_208': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_208': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_209': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_209': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_21': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_210': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_210': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_211': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_211': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_212': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_212': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_213': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_213': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_214': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_214': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_215': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_215': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_216': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_216': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_217': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_217': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_218': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_218': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_219': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_219': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_22': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_220': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_220': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_221': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_221': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_222': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_222': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_223': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_223': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_224': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_224': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_225': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_225': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_226': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_226': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_227': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_227': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_228': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_228': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_229': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_229': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_23': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_230': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_230': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_231': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_231': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_232': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_232': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_233': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_233': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_234': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_234': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_235': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_235': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_236': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_236': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_237': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_237': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_238': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_238': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_239': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_239': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_24': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_240': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_240': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_241': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_241': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_242': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_242': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_243': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_243': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_244': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_244': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_245': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_245': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_246': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_246': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_247': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_247': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_248': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_248': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_249': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_249': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_25': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_250': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_250': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_251': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_251': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_252': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_252': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_253': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_253': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_254': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_254': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_255': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_255': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_26': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_27': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_28': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_29': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_3': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_30': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_31': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_32': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_33': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_34': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_35': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_36': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_37': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_38': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_39': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_4': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_40': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_41': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_42': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_43': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_44': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_45': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_46': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_47': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_48': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_49': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_5': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_50': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_51': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_52': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_53': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_54': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_55': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_56': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_57': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_58': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_59': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_6': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_60': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_61': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_62': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_63': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_64': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_64': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_65': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_65': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_66': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_66': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_67': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_67': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_68': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_68': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_69': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_69': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_7': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_70': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_70': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_71': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_71': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_72': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_72': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_73': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_73': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_74': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_74': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_75': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_75': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_76': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_76': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_77': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_77': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_78': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_78': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_79': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_79': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_8': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_80': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_80': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_81': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_81': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_82': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_82': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_83': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_83': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_84': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_84': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_85': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_85': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_86': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_86': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_87': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_87': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_88': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_88': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_89': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_89': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_9': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_90': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_90': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_91': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_91': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_92': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_92': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_93': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_93': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_94': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_94': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_95': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_95': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_96': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_96': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_97': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_97': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_98': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_98': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_99': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_99': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'delay_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'spi_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'spi_clk': FREQ_HZ bus parameter is missing for output clock interface. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_fmcadc5_sync "bd/bd.tcl" -# ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface delay_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'delay_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'delay_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'delay_rst'. -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:14:33 2021... diff --git a/adi_library/axi_generic_adc/axi_generic_adc_ip.log b/adi_library/axi_generic_adc/axi_generic_adc_ip.log deleted file mode 100644 index 65623646..00000000 --- a/adi_library/axi_generic_adc/axi_generic_adc_ip.log +++ /dev/null @@ -1,1016 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_generic_adc_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_generic_adc -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_generic_adc [list \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "axi_generic_adc.v" \ -# ] -# adi_ip_properties axi_generic_adc -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(NUM_OF_CHANNELS - 1):0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:14:44 2021... diff --git a/adi_library/axi_generic_adc/vivado.jou b/adi_library/axi_generic_adc/vivado.jou deleted file mode 100644 index 3169e93f..00000000 --- a/adi_library/axi_generic_adc/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:14:33 2021 -# Process ID: 5559 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc -# Command line: vivado -mode batch -source axi_generic_adc_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc/vivado.jou -#----------------------------------------------------------- -source axi_generic_adc_ip.tcl diff --git a/adi_library/axi_generic_adc/vivado.log b/adi_library/axi_generic_adc/vivado.log deleted file mode 100644 index 24d1e827..00000000 --- a/adi_library/axi_generic_adc/vivado.log +++ /dev/null @@ -1,1021 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:14:33 2021 -# Process ID: 5559 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc -# Command line: vivado -mode batch -source axi_generic_adc_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc/vivado.jou -#----------------------------------------------------------- -source axi_generic_adc_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_generic_adc -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_generic_adc [list \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "axi_generic_adc.v" \ -# ] -# adi_ip_properties axi_generic_adc -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_generic_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(NUM_OF_CHANNELS - 1):0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:14:44 2021... diff --git a/adi_library/axi_gpreg/axi_gpreg_ip.log b/adi_library/axi_gpreg/axi_gpreg_ip.log deleted file mode 100644 index cdd26213..00000000 --- a/adi_library/axi_gpreg/axi_gpreg_ip.log +++ /dev/null @@ -1,1036 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_gpreg_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_gpreg -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_gpreg [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "axi_gpreg_io.v" \ -# "axi_gpreg_constr.ttcl" \ -# "axi_gpreg_clock_mon.v" \ -# "axi_gpreg.v" ] -# adi_ip_properties axi_gpreg -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg/axi_gpreg_constr.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_ttcl axi_gpreg "axi_gpreg_constr.ttcl" -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 0} \ -# [ipx::get_ports up_gp_*_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 1} \ -# [ipx::get_ports up_gp_*_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 2} \ -# [ipx::get_ports up_gp_*_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 3} \ -# [ipx::get_ports up_gp_*_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 4} \ -# [ipx::get_ports up_gp_*_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 5} \ -# [ipx::get_ports up_gp_*_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 6} \ -# [ipx::get_ports up_gp_*_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 7} \ -# [ipx::get_ports up_gp_*_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 0} \ -# [ipx::get_ports d_clk_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 1} \ -# [ipx::get_ports d_clk_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 2} \ -# [ipx::get_ports d_clk_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 3} \ -# [ipx::get_ports d_clk_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 4} \ -# [ipx::get_ports d_clk_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 5} \ -# [ipx::get_ports d_clk_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 6} \ -# [ipx::get_ports d_clk_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 7} \ -# [ipx::get_ports d_clk_7 -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:14:55 2021... diff --git a/adi_library/axi_gpreg/vivado.jou b/adi_library/axi_gpreg/vivado.jou deleted file mode 100644 index d1663065..00000000 --- a/adi_library/axi_gpreg/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:14:45 2021 -# Process ID: 5626 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg -# Command line: vivado -mode batch -source axi_gpreg_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg/vivado.jou -#----------------------------------------------------------- -source axi_gpreg_ip.tcl diff --git a/adi_library/axi_gpreg/vivado.log b/adi_library/axi_gpreg/vivado.log deleted file mode 100644 index b018a972..00000000 --- a/adi_library/axi_gpreg/vivado.log +++ /dev/null @@ -1,1041 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:14:45 2021 -# Process ID: 5626 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg -# Command line: vivado -mode batch -source axi_gpreg_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg/vivado.jou -#----------------------------------------------------------- -source axi_gpreg_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_gpreg -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_gpreg [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "axi_gpreg_io.v" \ -# "axi_gpreg_constr.ttcl" \ -# "axi_gpreg_clock_mon.v" \ -# "axi_gpreg.v" ] -# adi_ip_properties axi_gpreg -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg/axi_gpreg_constr.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_gpreg'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_ttcl axi_gpreg "axi_gpreg_constr.ttcl" -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 0} \ -# [ipx::get_ports up_gp_*_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 1} \ -# [ipx::get_ports up_gp_*_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 2} \ -# [ipx::get_ports up_gp_*_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 3} \ -# [ipx::get_ports up_gp_*_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 4} \ -# [ipx::get_ports up_gp_*_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 5} \ -# [ipx::get_ports up_gp_*_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 6} \ -# [ipx::get_ports up_gp_*_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 7} \ -# [ipx::get_ports up_gp_*_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 0} \ -# [ipx::get_ports d_clk_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 1} \ -# [ipx::get_ports d_clk_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 2} \ -# [ipx::get_ports d_clk_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 3} \ -# [ipx::get_ports d_clk_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 4} \ -# [ipx::get_ports d_clk_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 5} \ -# [ipx::get_ports d_clk_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 6} \ -# [ipx::get_ports d_clk_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 7} \ -# [ipx::get_ports d_clk_7 -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:14:55 2021... diff --git a/adi_library/axi_hdmi_rx/axi_hdmi_rx_ip.log b/adi_library/axi_hdmi_rx/axi_hdmi_rx_ip.log deleted file mode 100644 index 08caab0e..00000000 --- a/adi_library/axi_hdmi_rx/axi_hdmi_rx_ip.log +++ /dev/null @@ -1,1378 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_hdmi_rx_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_hdmi_rx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_hdmi_rx [list \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/ad_csc.v" \ -# "$ad_hdl_dir/library/common/ad_ss_422to444.v" \ -# "$ad_hdl_dir/library/common/ad_csc_CrYCb2RGB.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_hdmi_rx.v" \ -# "axi_hdmi_rx.v" \ -# "axi_hdmi_rx_es.v" \ -# "axi_hdmi_rx_tpm.v" \ -# "axi_hdmi_rx_core.v" ] -# adi_ip_properties axi_hdmi_rx -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc_CrYCb2RGB.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_ss_422to444.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_hdmi_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc_CrYCb2RGB.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_ss_422to444.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_hdmi_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'hdmi_dma'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'hdmi_dma'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'hdmi_dma'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'hdmi_dma'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'hdmi_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'hdmi_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'hdmi_rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface hdmi_rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface hdmi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:15:10 2021... diff --git a/adi_library/axi_hdmi_rx/vivado.jou b/adi_library/axi_hdmi_rx/vivado.jou deleted file mode 100644 index 5a377fb2..00000000 --- a/adi_library/axi_hdmi_rx/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:14:56 2021 -# Process ID: 5694 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx -# Command line: vivado -mode batch -source axi_hdmi_rx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx/vivado.jou -#----------------------------------------------------------- -source axi_hdmi_rx_ip.tcl diff --git a/adi_library/axi_hdmi_rx/vivado.log b/adi_library/axi_hdmi_rx/vivado.log deleted file mode 100644 index 51e2ce47..00000000 --- a/adi_library/axi_hdmi_rx/vivado.log +++ /dev/null @@ -1,1383 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:14:56 2021 -# Process ID: 5694 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx -# Command line: vivado -mode batch -source axi_hdmi_rx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx/vivado.jou -#----------------------------------------------------------- -source axi_hdmi_rx_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_hdmi_rx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_hdmi_rx [list \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/ad_csc.v" \ -# "$ad_hdl_dir/library/common/ad_ss_422to444.v" \ -# "$ad_hdl_dir/library/common/ad_csc_CrYCb2RGB.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_hdmi_rx.v" \ -# "axi_hdmi_rx.v" \ -# "axi_hdmi_rx_es.v" \ -# "axi_hdmi_rx_tpm.v" \ -# "axi_hdmi_rx_core.v" ] -# adi_ip_properties axi_hdmi_rx -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc_CrYCb2RGB.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_ss_422to444.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_hdmi_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc_CrYCb2RGB.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_ss_422to444.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_hdmi_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'hdmi_dma'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_dma_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_rx_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'hdmi_dma'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'hdmi_dma'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'hdmi_dma'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_rx'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_dma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_dma_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_rx_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'hdmi_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'hdmi_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'hdmi_rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface hdmi_rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface hdmi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:15:10 2021... diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx_ip.log b/adi_library/axi_hdmi_tx/axi_hdmi_tx_ip.log deleted file mode 100644 index 14a0e645..00000000 --- a/adi_library/axi_hdmi_tx/axi_hdmi_tx_ip.log +++ /dev/null @@ -1,1401 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_hdmi_tx_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_hdmi_tx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_hdmi_tx [list \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/ad_csc.v" \ -# "$ad_hdl_dir/library/common/ad_csc_RGB2CrYCb.v" \ -# "$ad_hdl_dir/library/common/ad_ss_444to422.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_hdmi_tx.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_hdmi_tx_constr.xdc" \ -# "axi_hdmi_tx_vdma.v" \ -# "axi_hdmi_tx_es.v" \ -# "axi_hdmi_tx_core.v" \ -# "axi_hdmi_tx.v" ] -# adi_ip_properties axi_hdmi_tx -WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v'. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc_RGB2CrYCb.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_ss_444to422.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_hdmi_tx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc_RGB2CrYCb.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_ss_444to422.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_hdmi_tx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_16'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_16_es'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '23:0' is present in all ports of the interface 'hdmi_24'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '35:0' is present in all ports of the interface 'hdmi_36'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'vdma'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_e' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_e' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_e' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'vdma_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'vdma_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'vdma_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'vdma_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'vdma_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_16'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_16_es'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '23:0' is present in all ports of the interface 'hdmi_24'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '35:0' is present in all ports of the interface 'hdmi_36'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data_e' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_e': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data_e' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_e': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data_e' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_e': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'vdma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'vdma_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'hdmi_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'hdmi_out_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'hdmi_out_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'vdma_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_hdmi_tx "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *hsync* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *vsync* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *data* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *es_data* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *vdma_end_of_frame* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *vdma_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *vdma_data* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *vdma_ready* -of_objects [ipx::current_core]] -# set_property value_format string [ipx::get_user_parameters INTERFACE -of_objects [ipx::current_core]] -# set_property value_format string [ipx::get_hdl_parameters INTERFACE -of_objects [ipx::current_core]] -# set_property value_validation_list {16_BIT 24_BIT 36_BIT 16_BIT_EMBEDDED_SYNC} \ -# [ipx::get_user_parameters INTERFACE -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT"} \ -# [ipx::get_ports *hdmi_16* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "24_BIT"} \ -# [ipx::get_ports *hdmi_24* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "36_BIT"} \ -# [ipx::get_ports *hdmi_36* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT_EMBEDDED_SYNC"} \ -# [ipx::get_ports *hdmi_16_es_data* -of_objects [ipx::current_core]] -# adi_add_bus "s_axis" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"vdma_ready" "TREADY"} \ -# {"vdma_valid" "TVALID"} \ -# {"vdma_data" "TDATA"} \ -# {"vdma_end_of_frame" "TLAST"} ] -# ipx::infer_bus_interface hdmi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface hdmi_out_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_out_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface vdma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'vdma_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::associate_bus_interfaces -busif s_axis -clock vdma_clk [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'vdma_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis'. -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:23:17 2021... diff --git a/adi_library/axi_hdmi_tx/vivado.jou b/adi_library/axi_hdmi_tx/vivado.jou deleted file mode 100644 index 380b2899..00000000 --- a/adi_library/axi_hdmi_tx/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:23:00 2021 -# Process ID: 66684 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx -# Command line: vivado -mode batch -source axi_hdmi_tx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx/vivado.jou -#----------------------------------------------------------- -source axi_hdmi_tx_ip.tcl diff --git a/adi_library/axi_hdmi_tx/vivado.log b/adi_library/axi_hdmi_tx/vivado.log deleted file mode 100644 index ecef9947..00000000 --- a/adi_library/axi_hdmi_tx/vivado.log +++ /dev/null @@ -1,1406 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:23:00 2021 -# Process ID: 66684 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx -# Command line: vivado -mode batch -source axi_hdmi_tx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx/vivado.jou -#----------------------------------------------------------- -source axi_hdmi_tx_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_hdmi_tx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_hdmi_tx [list \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/ad_csc.v" \ -# "$ad_hdl_dir/library/common/ad_csc_RGB2CrYCb.v" \ -# "$ad_hdl_dir/library/common/ad_ss_444to422.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_hdmi_tx.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_hdmi_tx_constr.xdc" \ -# "axi_hdmi_tx_vdma.v" \ -# "axi_hdmi_tx_es.v" \ -# "axi_hdmi_tx_core.v" \ -# "axi_hdmi_tx.v" ] -# adi_ip_properties axi_hdmi_tx -WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v'. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc_RGB2CrYCb.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_ss_444to422.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_hdmi_tx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_csc_RGB2CrYCb.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_ss_444to422.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_hdmi_tx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_16'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_16_es'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '23:0' is present in all ports of the interface 'hdmi_24'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '35:0' is present in all ports of the interface 'hdmi_36'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'vdma'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_e' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_16_es_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_24_e' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_36_e' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'vdma_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'vdma_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'vdma_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'vdma_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'vdma_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_16'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'hdmi_16_es'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '23:0' is present in all ports of the interface 'hdmi_24'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '35:0' is present in all ports of the interface 'hdmi_36'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_data_e' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_e': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_16_es_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_16_es_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_24_data_e' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_24_e': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'hdmi_36_data_e' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'hdmi_36_e': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'vdma_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'vdma_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'vdma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'hdmi_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'hdmi_out_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'hdmi_out_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'vdma_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd axi_hdmi_tx "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports *hsync* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *vsync* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *data* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *es_data* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *vdma_end_of_frame* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *vdma_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *vdma_data* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *vdma_ready* -of_objects [ipx::current_core]] -# set_property value_format string [ipx::get_user_parameters INTERFACE -of_objects [ipx::current_core]] -# set_property value_format string [ipx::get_hdl_parameters INTERFACE -of_objects [ipx::current_core]] -# set_property value_validation_list {16_BIT 24_BIT 36_BIT 16_BIT_EMBEDDED_SYNC} \ -# [ipx::get_user_parameters INTERFACE -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT"} \ -# [ipx::get_ports *hdmi_16* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "24_BIT"} \ -# [ipx::get_ports *hdmi_24* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "36_BIT"} \ -# [ipx::get_ports *hdmi_36* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT_EMBEDDED_SYNC"} \ -# [ipx::get_ports *hdmi_16_es_data* -of_objects [ipx::current_core]] -# adi_add_bus "s_axis" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"vdma_ready" "TREADY"} \ -# {"vdma_valid" "TVALID"} \ -# {"vdma_data" "TDATA"} \ -# {"vdma_end_of_frame" "TLAST"} ] -# ipx::infer_bus_interface hdmi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface hdmi_out_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'hdmi_out_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface vdma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'vdma_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::associate_bus_interfaces -busif s_axis -clock vdma_clk [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'vdma_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis'. -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:23:17 2021... diff --git a/adi_library/axi_i2s_adi/axi_i2s_adi_ip.log b/adi_library/axi_i2s_adi/axi_i2s_adi_ip.log deleted file mode 100644 index 6fc9cb8c..00000000 --- a/adi_library/axi_i2s_adi/axi_i2s_adi_ip.log +++ /dev/null @@ -1,943 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_i2s_adi_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_i2s_adi -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_i2s_adi [list \ -# "$ad_hdl_dir/library/common/axi_ctrlif.vhd" \ -# "$ad_hdl_dir/library/common/axi_streaming_dma_tx_fifo.vhd" \ -# "$ad_hdl_dir/library/common/axi_streaming_dma_rx_fifo.vhd" \ -# "$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \ -# "$ad_hdl_dir/library/common/dma_fifo.vhd" \ -# "i2s_controller.vhd" \ -# "i2s_rx.vhd" \ -# "i2s_tx.vhd" \ -# "i2s_clkgen.vhd" \ -# "fifo_synchronizer.vhd" \ -# "axi_i2s_adi.vhd" \ -# "axi_i2s_adi_constr.xdc" \ -# ] -# adi_ip_properties axi_i2s_adi -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_rx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_tx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_rx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_tx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rx_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_tx_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rx_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_tx_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rx_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_tx_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rx_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rx_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_tx_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_tx_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axis_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3157] Bus Interface 'dma_req_rx_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'dma_req_rx_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3157] Bus Interface 'dma_req_tx_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'dma_req_tx_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_req_rx_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_req_tx_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# set_property PROCESSING_ORDER LATE [ipx::get_files axi_i2s_adi_constr.xdc \ -# -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \ -# -filter {NAME =~ *synthesis*}]] -# adi_ip_infer_streaming_interfaces axi_i2s_adi -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rx_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_tx_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rx_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_tx_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rx_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_tx_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rx_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rx_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_tx_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_tx_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axis_aresetn'. -# set_property display_name "ADI AXI I2S Controller" [ipx::current_core] -# set_property description "ADI AXI I2S Controller" [ipx::current_core] -# adi_add_bus "dma_ack_rx" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { \ -# {"dma_req_rx_davalid" "TVALID"} \ -# {"dma_req_rx_daready" "TREADY"} \ -# {"dma_req_rx_datype" "TUSER"} \ -# } -# adi_add_bus "dma_req_rx" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { \ -# {"dma_req_rx_drvalid" "TVALID"} \ -# {"dma_req_rx_drready" "TREADY"} \ -# {"dma_req_rx_drtype" "TUSER"} \ -# {"dma_req_rx_drlast" "TLAST"} \ -# } -# adi_add_bus_clock "dma_req_rx_aclk" "dma_req_rx:dma_ack_rx" "dma_req_rx_rstn" -# adi_add_bus "dma_ack_tx" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { \ -# {"dma_req_tx_davalid" "TVALID"} \ -# {"dma_req_tx_daready" "TREADY"} \ -# {"dma_req_tx_datype" "TUSER"} \ -# } -# adi_add_bus "dma_req_tx" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { \ -# {"dma_req_tx_drvalid" "TVALID"} \ -# {"dma_req_tx_drready" "TREADY"} \ -# {"dma_req_tx_drtype" "TUSER"} \ -# {"dma_req_tx_drlast" "TLAST"} \ -# } -# adi_add_bus_clock "dma_req_tx_aclk" "dma_req_tx:dma_ack_tx" "dma_req_tx_rstn" -# adi_add_bus "i2s" "master" \ -# "analog.com:interface:i2s_rtl:1.0" \ -# "analog.com:interface:i2s:1.0" \ -# { \ -# {"bclk_o" "BCLK"} \ -# {"lrclk_o" "LRCLK"} \ -# {"sdata_o" "SDATA_OUT"} \ -# {"sdata_i" "SDATA_IN"} \ -# } -# adi_add_bus_clock "data_clk_i" "i2s" -# adi_set_bus_dependency "s_axis" "s_axis" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" -# adi_set_bus_dependency "m_axis" "m_axis" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" -# adi_set_bus_dependency "dma_ack_tx" "dma_req_tx_da" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" -# adi_set_bus_dependency "dma_req_tx" "dma_req_tx_dr" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" -# adi_set_ports_dependency "dma_req_tx_aclk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" -# adi_set_ports_dependency "dma_req_tx_rstn" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" -# adi_set_bus_dependency "dma_ack_rx" "dma_req_rx_da" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" -# adi_set_bus_dependency "dma_req_rx" "dma_req_rx_dr" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" -# adi_set_ports_dependency "dma_req_rx_aclk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" -# adi_set_ports_dependency "dma_req_rx_rstn" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" -# set_property driver_value 0 [ipx::get_ports -filter "direction==in && enablement_dependency!={}" -of_objects [ipx::current_core]] -# set cc [ipx::current_core] -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_list" "16 20 24 32" \ -# ] \ -# [ipx::get_user_parameters SLOT_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "pairs" \ -# "value_validation_pairs" { \ -# "Falling Edge" "0" \ -# "Rising Edge" "1" \ -# } \ -# ] \ -# [ipx::get_user_parameters LRCLK_POL -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "pairs" \ -# "value_validation_pairs" { \ -# "Falling Edge" "0" \ -# "Rising Edge" "1" \ -# } \ -# ] \ -# [ipx::get_user_parameters BCLK_POL -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "pairs" \ -# "value_validation_pairs" { \ -# "AXI Stream" "0" \ -# "PL330" "1" \ -# } \ -# ] \ -# [ipx::get_user_parameters DMA_TYPE -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "1" \ -# ] \ -# [ipx::get_user_parameters HAS_RX -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "1" \ -# ] \ -# [ipx::get_user_parameters HAS_TX -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "32" \ -# ] \ -# [ipx::get_user_parameters NUM_OF_CHANNEL -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "32" \ -# ] \ -# [ipx::get_user_parameters S_AXI_ADDRESS_WIDTH -of_objects $cc] -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set i2s_group [ipgui::add_group -name "I2S Configuration" -component $cc \ -# -parent $page0 -display_name "I2S Configuration"] -# set p [ipgui::get_guiparamspec -name "SLOT_WIDTH" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $i2s_group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "Slot Width" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "LRCLK_POL" -component $cc] -# ipgui::move_param -component $cc -order 1 $p -parent $i2s_group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "Left-Right Clock Polarity" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "BCLK_POL" -component $cc] -# ipgui::move_param -component $cc -order 2 $p -parent $i2s_group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "Bit Clock Polarity" \ -# ] $p -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration"] -# set p [ipgui::get_guiparamspec -name "HAS_RX" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $general_group -# set_property -dict [list \ -# "widget" "checkBox" \ -# "display_name" "Enable I2S Receiver Support" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "HAS_TX" -component $cc] -# ipgui::move_param -component $cc -order 1 $p -parent $general_group -# set_property -dict [list \ -# "widget" "checkBox" \ -# "display_name" "Enable I2S Transmitter Support" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "DMA_TYPE" -component $cc] -# ipgui::move_param -component $cc -order 2 $p -parent $general_group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "DMA Interface Type" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "NUM_OF_CHANNEL" -component $cc] -# ipgui::move_param -component $cc -order 3 $p -parent $general_group -# set_property -dict [list \ -# "display_name" "Number of Audio Channels" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "S_AXI_ADDRESS_WIDTH" -component $cc] -# ipgui::move_param -component $cc -order 4 $p -parent $general_group -# set_property -dict [list \ -# "display_name" "AXI Address Width" \ -# ] $p -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "S_AXI_DATA_WIDTH" -component $cc] -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DEVICE_FAMILY" -component $cc] -# ipx::create_xgui_files $cc -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:15:23 2021... diff --git a/adi_library/axi_i2s_adi/vivado.jou b/adi_library/axi_i2s_adi/vivado.jou deleted file mode 100644 index c7883b98..00000000 --- a/adi_library/axi_i2s_adi/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:15:11 2021 -# Process ID: 5779 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi -# Command line: vivado -mode batch -source axi_i2s_adi_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi/vivado.jou -#----------------------------------------------------------- -source axi_i2s_adi_ip.tcl diff --git a/adi_library/axi_i2s_adi/vivado.log b/adi_library/axi_i2s_adi/vivado.log deleted file mode 100644 index 491aa7a9..00000000 --- a/adi_library/axi_i2s_adi/vivado.log +++ /dev/null @@ -1,948 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:15:11 2021 -# Process ID: 5779 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi -# Command line: vivado -mode batch -source axi_i2s_adi_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi/vivado.jou -#----------------------------------------------------------- -source axi_i2s_adi_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_i2s_adi -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_i2s_adi [list \ -# "$ad_hdl_dir/library/common/axi_ctrlif.vhd" \ -# "$ad_hdl_dir/library/common/axi_streaming_dma_tx_fifo.vhd" \ -# "$ad_hdl_dir/library/common/axi_streaming_dma_rx_fifo.vhd" \ -# "$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \ -# "$ad_hdl_dir/library/common/dma_fifo.vhd" \ -# "i2s_controller.vhd" \ -# "i2s_rx.vhd" \ -# "i2s_tx.vhd" \ -# "i2s_clkgen.vhd" \ -# "fifo_synchronizer.vhd" \ -# "axi_i2s_adi.vhd" \ -# "axi_i2s_adi_constr.xdc" \ -# ] -# adi_ip_properties axi_i2s_adi -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_rx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_tx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_rx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_tx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rx_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_tx_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rx_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_tx_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rx_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_tx_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rx_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rx_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_tx_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_tx_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axis_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3157] Bus Interface 'dma_req_rx_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'dma_req_rx_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3157] Bus Interface 'dma_req_tx_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'dma_req_tx_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_req_rx_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_req_tx_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# set_property PROCESSING_ORDER LATE [ipx::get_files axi_i2s_adi_constr.xdc \ -# -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \ -# -filter {NAME =~ *synthesis*}]] -# adi_ip_infer_streaming_interfaces axi_i2s_adi -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rx_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_tx_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rx_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_tx_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rx_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_tx_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rx_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rx_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_tx_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_tx_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axis_aresetn'. -# set_property display_name "ADI AXI I2S Controller" [ipx::current_core] -# set_property description "ADI AXI I2S Controller" [ipx::current_core] -# adi_add_bus "dma_ack_rx" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { \ -# {"dma_req_rx_davalid" "TVALID"} \ -# {"dma_req_rx_daready" "TREADY"} \ -# {"dma_req_rx_datype" "TUSER"} \ -# } -# adi_add_bus "dma_req_rx" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { \ -# {"dma_req_rx_drvalid" "TVALID"} \ -# {"dma_req_rx_drready" "TREADY"} \ -# {"dma_req_rx_drtype" "TUSER"} \ -# {"dma_req_rx_drlast" "TLAST"} \ -# } -# adi_add_bus_clock "dma_req_rx_aclk" "dma_req_rx:dma_ack_rx" "dma_req_rx_rstn" -# adi_add_bus "dma_ack_tx" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { \ -# {"dma_req_tx_davalid" "TVALID"} \ -# {"dma_req_tx_daready" "TREADY"} \ -# {"dma_req_tx_datype" "TUSER"} \ -# } -# adi_add_bus "dma_req_tx" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { \ -# {"dma_req_tx_drvalid" "TVALID"} \ -# {"dma_req_tx_drready" "TREADY"} \ -# {"dma_req_tx_drtype" "TUSER"} \ -# {"dma_req_tx_drlast" "TLAST"} \ -# } -# adi_add_bus_clock "dma_req_tx_aclk" "dma_req_tx:dma_ack_tx" "dma_req_tx_rstn" -# adi_add_bus "i2s" "master" \ -# "analog.com:interface:i2s_rtl:1.0" \ -# "analog.com:interface:i2s:1.0" \ -# { \ -# {"bclk_o" "BCLK"} \ -# {"lrclk_o" "LRCLK"} \ -# {"sdata_o" "SDATA_OUT"} \ -# {"sdata_i" "SDATA_IN"} \ -# } -# adi_add_bus_clock "data_clk_i" "i2s" -# adi_set_bus_dependency "s_axis" "s_axis" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" -# adi_set_bus_dependency "m_axis" "m_axis" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" -# adi_set_bus_dependency "dma_ack_tx" "dma_req_tx_da" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" -# adi_set_bus_dependency "dma_req_tx" "dma_req_tx_dr" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" -# adi_set_ports_dependency "dma_req_tx_aclk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" -# adi_set_ports_dependency "dma_req_tx_rstn" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" -# adi_set_bus_dependency "dma_ack_rx" "dma_req_rx_da" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" -# adi_set_bus_dependency "dma_req_rx" "dma_req_rx_dr" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" -# adi_set_ports_dependency "dma_req_rx_aclk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" -# adi_set_ports_dependency "dma_req_rx_rstn" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" -# set_property driver_value 0 [ipx::get_ports -filter "direction==in && enablement_dependency!={}" -of_objects [ipx::current_core]] -# set cc [ipx::current_core] -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_list" "16 20 24 32" \ -# ] \ -# [ipx::get_user_parameters SLOT_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "pairs" \ -# "value_validation_pairs" { \ -# "Falling Edge" "0" \ -# "Rising Edge" "1" \ -# } \ -# ] \ -# [ipx::get_user_parameters LRCLK_POL -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "pairs" \ -# "value_validation_pairs" { \ -# "Falling Edge" "0" \ -# "Rising Edge" "1" \ -# } \ -# ] \ -# [ipx::get_user_parameters BCLK_POL -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "pairs" \ -# "value_validation_pairs" { \ -# "AXI Stream" "0" \ -# "PL330" "1" \ -# } \ -# ] \ -# [ipx::get_user_parameters DMA_TYPE -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "1" \ -# ] \ -# [ipx::get_user_parameters HAS_RX -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "1" \ -# ] \ -# [ipx::get_user_parameters HAS_TX -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "32" \ -# ] \ -# [ipx::get_user_parameters NUM_OF_CHANNEL -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "32" \ -# ] \ -# [ipx::get_user_parameters S_AXI_ADDRESS_WIDTH -of_objects $cc] -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set i2s_group [ipgui::add_group -name "I2S Configuration" -component $cc \ -# -parent $page0 -display_name "I2S Configuration"] -# set p [ipgui::get_guiparamspec -name "SLOT_WIDTH" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $i2s_group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "Slot Width" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "LRCLK_POL" -component $cc] -# ipgui::move_param -component $cc -order 1 $p -parent $i2s_group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "Left-Right Clock Polarity" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "BCLK_POL" -component $cc] -# ipgui::move_param -component $cc -order 2 $p -parent $i2s_group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "Bit Clock Polarity" \ -# ] $p -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration"] -# set p [ipgui::get_guiparamspec -name "HAS_RX" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $general_group -# set_property -dict [list \ -# "widget" "checkBox" \ -# "display_name" "Enable I2S Receiver Support" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "HAS_TX" -component $cc] -# ipgui::move_param -component $cc -order 1 $p -parent $general_group -# set_property -dict [list \ -# "widget" "checkBox" \ -# "display_name" "Enable I2S Transmitter Support" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "DMA_TYPE" -component $cc] -# ipgui::move_param -component $cc -order 2 $p -parent $general_group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "DMA Interface Type" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "NUM_OF_CHANNEL" -component $cc] -# ipgui::move_param -component $cc -order 3 $p -parent $general_group -# set_property -dict [list \ -# "display_name" "Number of Audio Channels" \ -# ] $p -# set p [ipgui::get_guiparamspec -name "S_AXI_ADDRESS_WIDTH" -component $cc] -# ipgui::move_param -component $cc -order 4 $p -parent $general_group -# set_property -dict [list \ -# "display_name" "AXI Address Width" \ -# ] $p -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "S_AXI_DATA_WIDTH" -component $cc] -# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DEVICE_FAMILY" -component $cc] -# ipx::create_xgui_files $cc -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:15:23 2021... diff --git a/adi_library/axi_intr_monitor/axi_intr_monitor_ip.log b/adi_library/axi_intr_monitor/axi_intr_monitor_ip.log deleted file mode 100644 index 33e50c27..00000000 --- a/adi_library/axi_intr_monitor/axi_intr_monitor_ip.log +++ /dev/null @@ -1,995 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_intr_monitor_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_intr_monitor -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_intr_monitor'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_intr_monitor [list \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "axi_intr_monitor.v" ] -# adi_ip_properties axi_intr_monitor -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_intr_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_intr_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:15:31 2021... diff --git a/adi_library/axi_intr_monitor/vivado.jou b/adi_library/axi_intr_monitor/vivado.jou deleted file mode 100644 index 1d36357a..00000000 --- a/adi_library/axi_intr_monitor/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:15:24 2021 -# Process ID: 5851 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_intr_monitor -# Command line: vivado -mode batch -source axi_intr_monitor_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_intr_monitor/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_intr_monitor/vivado.jou -#----------------------------------------------------------- -source axi_intr_monitor_ip.tcl diff --git a/adi_library/axi_intr_monitor/vivado.log b/adi_library/axi_intr_monitor/vivado.log deleted file mode 100644 index 03a3669a..00000000 --- a/adi_library/axi_intr_monitor/vivado.log +++ /dev/null @@ -1,1000 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:15:24 2021 -# Process ID: 5851 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_intr_monitor -# Command line: vivado -mode batch -source axi_intr_monitor_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_intr_monitor/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_intr_monitor/vivado.jou -#----------------------------------------------------------- -source axi_intr_monitor_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_intr_monitor -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_intr_monitor'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_intr_monitor [list \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "axi_intr_monitor.v" ] -# adi_ip_properties axi_intr_monitor -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_intr_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_intr_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:15:31 2021... diff --git a/adi_library/axi_laser_driver/axi_laser_driver_ip.log b/adi_library/axi_laser_driver/axi_laser_driver_ip.log deleted file mode 100644 index e3ac454d..00000000 --- a/adi_library/axi_laser_driver/axi_laser_driver_ip.log +++ /dev/null @@ -1,766 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_laser_driver_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_laser_driver -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_laser_driver [list \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_laser_driver_constr.xdc" \ -# "axi_laser_driver_regmap.v" \ -# "axi_laser_driver.v"] -# adi_ip_properties axi_laser_driver -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'driver_n' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'driver_dp_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ext_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'driver_en_n' and definition port 'EN'. -WARNING: [IP_Flow 19-1965] Bus Interface 'driver_n': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ext_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_ttcl axi_laser_driver "../axi_pulse_gen/axi_pulse_gen_constr.ttcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# analog.com:user:axi_pulse_gen:1.0 \ -# } -# set cc [ipx::current_core] -# set_property display_name "ADI AXI Laser Driver" $cc -# set_property description "ADI AXI Laser Driver" $cc -# adi_add_bus ext_clk slave \ -# "xilinx.com:signal:clock_rtl:1.0" \ -# "xilinx.com:signal:clock:1.0" \ -# [list {"ext_clk" "CLK"} ] -# adi_set_ports_dependency "ext_clk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.ASYNC_CLK_EN')) = 1)" 0 -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "true" \ -# ] \ -# [ipx::get_user_parameters ASYNC_CLK_EN -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "true" \ -# ] \ -# [ipx::get_hdl_parameters ASYNC_CLK_EN -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "2147483647" \ -# ] \ -# [ipx::get_user_parameters PULSE_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "2147483647" \ -# ] \ -# [ipx::get_user_parameters PULSE_PERIOD -of_objects $cc] -# ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] -# ipx::save_core $cc -# ipgui::add_page -name {AXI Pulse Generator} -component $cc -display_name {AXI Pulse Generator} -# set page0 [ipgui::get_pagespec -name "AXI Pulse Generator" -component $cc] -# ipgui::add_param -name "ASYNC_CLK_EN" -component $cc -parent $page0 -# set_property -dict [list \ -# "display_name" "ASYNC_CLK_EN" \ -# "tooltip" "External clock for the counter" \ -# "widget" "checkBox" \ -# ] [ipgui::get_guiparamspec -name "ASYNC_CLK_EN" -component $cc] -# ipgui::add_param -name "PULSE_WIDTH" -component $cc -parent $page0 -# set_property -dict [list \ -# "display_name" "Pulse width" \ -# "tooltip" "Pulse width of the generated signal. The unit interval is the system or external clock period." \ -# ] [ipgui::get_guiparamspec -name "PULSE_WIDTH" -component $cc] -# ipgui::add_param -name "PULSE_PERIOD" -component $cc -parent $page0 -# set_property -dict [list \ -# "display_name" "Pulse period" \ -# "tooltip" "Period of the generated signal. The unit interval is the system or external clock period." \ -# ] [ipgui::get_guiparamspec -name "PULSE_PERIOD" -component $cc] -# ipx::create_xgui_files $cc -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:14 2021... diff --git a/adi_library/axi_laser_driver/vivado.jou b/adi_library/axi_laser_driver/vivado.jou deleted file mode 100644 index 40ccab55..00000000 --- a/adi_library/axi_laser_driver/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:24:06 2021 -# Process ID: 145620 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver -# Command line: vivado -mode batch -source axi_laser_driver_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver/vivado.jou -#----------------------------------------------------------- -source axi_laser_driver_ip.tcl diff --git a/adi_library/axi_laser_driver/vivado.log b/adi_library/axi_laser_driver/vivado.log deleted file mode 100644 index 96930532..00000000 --- a/adi_library/axi_laser_driver/vivado.log +++ /dev/null @@ -1,771 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:24:06 2021 -# Process ID: 145620 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver -# Command line: vivado -mode batch -source axi_laser_driver_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver/vivado.jou -#----------------------------------------------------------- -source axi_laser_driver_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_laser_driver -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_laser_driver [list \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "axi_laser_driver_constr.xdc" \ -# "axi_laser_driver_regmap.v" \ -# "axi_laser_driver.v"] -# adi_ip_properties axi_laser_driver -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'driver_n' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'driver_dp_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ext_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'driver_en_n' and definition port 'EN'. -WARNING: [IP_Flow 19-1965] Bus Interface 'driver_n': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ext_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_ttcl axi_laser_driver "../axi_pulse_gen/axi_pulse_gen_constr.ttcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# analog.com:user:axi_pulse_gen:1.0 \ -# } -# set cc [ipx::current_core] -# set_property display_name "ADI AXI Laser Driver" $cc -# set_property description "ADI AXI Laser Driver" $cc -# adi_add_bus ext_clk slave \ -# "xilinx.com:signal:clock_rtl:1.0" \ -# "xilinx.com:signal:clock:1.0" \ -# [list {"ext_clk" "CLK"} ] -# adi_set_ports_dependency "ext_clk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.ASYNC_CLK_EN')) = 1)" 0 -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "true" \ -# ] \ -# [ipx::get_user_parameters ASYNC_CLK_EN -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "true" \ -# ] \ -# [ipx::get_hdl_parameters ASYNC_CLK_EN -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "2147483647" \ -# ] \ -# [ipx::get_user_parameters PULSE_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "2147483647" \ -# ] \ -# [ipx::get_user_parameters PULSE_PERIOD -of_objects $cc] -# ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] -# ipx::save_core $cc -# ipgui::add_page -name {AXI Pulse Generator} -component $cc -display_name {AXI Pulse Generator} -# set page0 [ipgui::get_pagespec -name "AXI Pulse Generator" -component $cc] -# ipgui::add_param -name "ASYNC_CLK_EN" -component $cc -parent $page0 -# set_property -dict [list \ -# "display_name" "ASYNC_CLK_EN" \ -# "tooltip" "External clock for the counter" \ -# "widget" "checkBox" \ -# ] [ipgui::get_guiparamspec -name "ASYNC_CLK_EN" -component $cc] -# ipgui::add_param -name "PULSE_WIDTH" -component $cc -parent $page0 -# set_property -dict [list \ -# "display_name" "Pulse width" \ -# "tooltip" "Pulse width of the generated signal. The unit interval is the system or external clock period." \ -# ] [ipgui::get_guiparamspec -name "PULSE_WIDTH" -component $cc] -# ipgui::add_param -name "PULSE_PERIOD" -component $cc -parent $page0 -# set_property -dict [list \ -# "display_name" "Pulse period" \ -# "tooltip" "Period of the generated signal. The unit interval is the system or external clock period." \ -# ] [ipgui::get_guiparamspec -name "PULSE_PERIOD" -component $cc] -# ipx::create_xgui_files $cc -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:14 2021... diff --git a/adi_library/axi_logic_analyzer/axi_logic_analyzer_ip.log b/adi_library/axi_logic_analyzer/axi_logic_analyzer_ip.log deleted file mode 100644 index 692a536b..00000000 --- a/adi_library/axi_logic_analyzer/axi_logic_analyzer_ip.log +++ /dev/null @@ -1,1166 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_logic_analyzer_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_logic_analyzer -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_logic_analyzer [list \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "axi_logic_analyzer_constr.xdc" \ -# "axi_logic_analyzer_reg.v" \ -# "axi_logic_analyzer_trigger.v" \ -# "axi_logic_analyzer.v" ] -# adi_ip_properties axi_logic_analyzer -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'external_decimation' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'external' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'external'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'external_decimation': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'external_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'external': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'external': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface clk_out xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_out' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:15:42 2021... diff --git a/adi_library/axi_logic_analyzer/vivado.jou b/adi_library/axi_logic_analyzer/vivado.jou deleted file mode 100644 index 1e0ae406..00000000 --- a/adi_library/axi_logic_analyzer/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:15:32 2021 -# Process ID: 5926 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer -# Command line: vivado -mode batch -source axi_logic_analyzer_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer/vivado.jou -#----------------------------------------------------------- -source axi_logic_analyzer_ip.tcl diff --git a/adi_library/axi_logic_analyzer/vivado.log b/adi_library/axi_logic_analyzer/vivado.log deleted file mode 100644 index f3ff8718..00000000 --- a/adi_library/axi_logic_analyzer/vivado.log +++ /dev/null @@ -1,1171 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:15:32 2021 -# Process ID: 5926 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer -# Command line: vivado -mode batch -source axi_logic_analyzer_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer/vivado.jou -#----------------------------------------------------------- -source axi_logic_analyzer_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_logic_analyzer -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_logic_analyzer [list \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "axi_logic_analyzer_constr.xdc" \ -# "axi_logic_analyzer_reg.v" \ -# "axi_logic_analyzer_trigger.v" \ -# "axi_logic_analyzer.v" ] -# adi_ip_properties axi_logic_analyzer -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_logic_analyzer'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'external_decimation' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'external' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'external'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'external_decimation': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'external_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'external': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'external': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface clk_out xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_out' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:15:42 2021... diff --git a/adi_library/axi_mc_controller/axi_mc_controller_ip.log b/adi_library/axi_mc_controller/axi_mc_controller_ip.log deleted file mode 100644 index 70a5e7d4..00000000 --- a/adi_library/axi_mc_controller/axi_mc_controller_ip.log +++ /dev/null @@ -1,1008 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_mc_controller_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_mc_controller -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_controller'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_mc_controller [list \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "motor_driver.v" \ -# "delay.v" \ -# "control_registers.v" \ -# "axi_mc_controller_constr.xdc" \ -# "axi_mc_controller.v" ] -# adi_ip_properties axi_mc_controller -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_controller'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_controller'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_clk' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fmc_o' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ref_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_clk': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fmc_en_o' and definition port 'EN'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fmc_o': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ref_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'ref_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface ctrl_data_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_data_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:15:52 2021... diff --git a/adi_library/axi_mc_controller/vivado.jou b/adi_library/axi_mc_controller/vivado.jou deleted file mode 100644 index b1cb4ba4..00000000 --- a/adi_library/axi_mc_controller/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:15:43 2021 -# Process ID: 5990 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_controller -# Command line: vivado -mode batch -source axi_mc_controller_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_controller/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_controller/vivado.jou -#----------------------------------------------------------- -source axi_mc_controller_ip.tcl diff --git a/adi_library/axi_mc_controller/vivado.log b/adi_library/axi_mc_controller/vivado.log deleted file mode 100644 index cb79c057..00000000 --- a/adi_library/axi_mc_controller/vivado.log +++ /dev/null @@ -1,1013 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:15:43 2021 -# Process ID: 5990 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_controller -# Command line: vivado -mode batch -source axi_mc_controller_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_controller/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_controller/vivado.jou -#----------------------------------------------------------- -source axi_mc_controller_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_mc_controller -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_controller'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_mc_controller [list \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "motor_driver.v" \ -# "delay.v" \ -# "control_registers.v" \ -# "axi_mc_controller_constr.xdc" \ -# "axi_mc_controller.v" ] -# adi_ip_properties axi_mc_controller -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_controller'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_controller'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_clk' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fmc_o' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ref_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_clk': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fmc_en_o' and definition port 'EN'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fmc_o': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ref_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'ref_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface ctrl_data_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_data_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:15:52 2021... diff --git a/adi_library/axi_mc_current_monitor/axi_mc_current_monitor_ip.log b/adi_library/axi_mc_current_monitor/axi_mc_current_monitor_ip.log deleted file mode 100644 index 6e6eb0e2..00000000 --- a/adi_library/axi_mc_current_monitor/axi_mc_current_monitor_ip.log +++ /dev/null @@ -1,1019 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_mc_current_monitor_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_mc_current_monitor -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_mc_current_monitor [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "dec256sinc24b.v" \ -# "ad7401.v" \ -# "axi_mc_current_monitor_constr.xdc" \ -# "axi_mc_current_monitor.v" ] -# adi_ip_properties axi_mc_current_monitor -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ref_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ref_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'ref_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk_i xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_i' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk_o xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_o' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:16:05 2021... diff --git a/adi_library/axi_mc_current_monitor/vivado.jou b/adi_library/axi_mc_current_monitor/vivado.jou deleted file mode 100644 index 3bf73d91..00000000 --- a/adi_library/axi_mc_current_monitor/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:15:53 2021 -# Process ID: 6050 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor -# Command line: vivado -mode batch -source axi_mc_current_monitor_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor/vivado.jou -#----------------------------------------------------------- -source axi_mc_current_monitor_ip.tcl diff --git a/adi_library/axi_mc_current_monitor/vivado.log b/adi_library/axi_mc_current_monitor/vivado.log deleted file mode 100644 index 772fc7c8..00000000 --- a/adi_library/axi_mc_current_monitor/vivado.log +++ /dev/null @@ -1,1024 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:15:53 2021 -# Process ID: 6050 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor -# Command line: vivado -mode batch -source axi_mc_current_monitor_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor/vivado.jou -#----------------------------------------------------------- -source axi_mc_current_monitor_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_mc_current_monitor -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_mc_current_monitor [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "dec256sinc24b.v" \ -# "ad7401.v" \ -# "axi_mc_current_monitor_constr.xdc" \ -# "axi_mc_current_monitor.v" ] -# adi_ip_properties axi_mc_current_monitor -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ref_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ref_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'ref_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk_i xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_i' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk_o xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk_o' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:16:05 2021... diff --git a/adi_library/axi_mc_speed/axi_mc_speed_ip.log b/adi_library/axi_mc_speed/axi_mc_speed_ip.log deleted file mode 100644 index e4b3c6ca..00000000 --- a/adi_library/axi_mc_speed/axi_mc_speed_ip.log +++ /dev/null @@ -1,1012 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_mc_speed_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_mc_speed -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_mc_speed [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "debouncer.v" \ -# "speed_detector.v" \ -# "delay_30_degrees.v" \ -# "axi_mc_speed.v" ] -# adi_ip_properties axi_mc_speed -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ref_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ref_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'ref_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:16:18 2021... diff --git a/adi_library/axi_mc_speed/vivado.jou b/adi_library/axi_mc_speed/vivado.jou deleted file mode 100644 index 52ab20f8..00000000 --- a/adi_library/axi_mc_speed/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:16:06 2021 -# Process ID: 6134 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed -# Command line: vivado -mode batch -source axi_mc_speed_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed/vivado.jou -#----------------------------------------------------------- -source axi_mc_speed_ip.tcl diff --git a/adi_library/axi_mc_speed/vivado.log b/adi_library/axi_mc_speed/vivado.log deleted file mode 100644 index 640c49b6..00000000 --- a/adi_library/axi_mc_speed/vivado.log +++ /dev/null @@ -1,1017 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:16:06 2021 -# Process ID: 6134 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed -# Command line: vivado -mode batch -source axi_mc_speed_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed/vivado.jou -#----------------------------------------------------------- -source axi_mc_speed_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_mc_speed -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_mc_speed [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "debouncer.v" \ -# "speed_detector.v" \ -# "delay_30_degrees.v" \ -# "axi_mc_speed.v" ] -# adi_ip_properties axi_mc_speed -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_speed'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ref_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ref_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'ref_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:16:18 2021... diff --git a/adi_library/axi_pulse_gen/axi_pulse_gen_ip.log b/adi_library/axi_pulse_gen/axi_pulse_gen_ip.log deleted file mode 100644 index 6cb7761f..00000000 --- a/adi_library/axi_pulse_gen/axi_pulse_gen_ip.log +++ /dev/null @@ -1,764 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_pulse_gen_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_pulse_gen -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_pulse_gen [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/common/util_pulse_gen.v" \ -# "axi_pulse_gen_constr.ttcl" \ -# "axi_pulse_gen_regmap.v" \ -# "axi_pulse_gen.v"] -# adi_ip_properties axi_pulse_gen -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen/axi_pulse_gen_constr.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ext_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3153] Bus Interface 'ext_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_ttcl axi_pulse_gen "axi_pulse_gen_constr.ttcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# } -# set cc [ipx::current_core] -# set_property display_name "ADI AXI Pulse Generator" $cc -# set_property description "ADI AXI Pulse Generator" $cc -# adi_add_bus ext_clk slave \ -# "xilinx.com:signal:clock_rtl:1.0" \ -# "xilinx.com:signal:clock:1.0" \ -# [list {"ext_clk" "CLK"} ] -# adi_set_ports_dependency "ext_clk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.ASYNC_CLK_EN')) = 1)" 0 -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "true" \ -# ] \ -# [ipx::get_user_parameters ASYNC_CLK_EN -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "true" \ -# ] \ -# [ipx::get_hdl_parameters ASYNC_CLK_EN -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "2147483647" \ -# ] \ -# [ipx::get_user_parameters PULSE_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "2147483647" \ -# ] \ -# [ipx::get_user_parameters PULSE_PERIOD -of_objects $cc] -# ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] -# ipx::save_core $cc -# ipgui::add_page -name {AXI Pulse Generator} -component $cc -display_name {AXI Pulse Generator} -# set page0 [ipgui::get_pagespec -name "AXI Pulse Generator" -component $cc] -# ipgui::add_param -name "ASYNC_CLK_EN" -component $cc -parent $page0 -# set_property -dict [list \ -# "display_name" "ASYNC_CLK_EN" \ -# "tooltip" "External clock for the counter" \ -# "widget" "checkBox" \ -# ] [ipgui::get_guiparamspec -name "ASYNC_CLK_EN" -component $cc] -# ipgui::add_param -name "PULSE_WIDTH" -component $cc -parent $page0 -# set_property -dict [list \ -# "display_name" "Pulse width" \ -# "tooltip" "Pulse width of the generated signal. The unit interval is the system or external clock period." \ -# ] [ipgui::get_guiparamspec -name "PULSE_WIDTH" -component $cc] -# ipgui::add_param -name "PULSE_PERIOD" -component $cc -parent $page0 -# set_property -dict [list \ -# "display_name" "Pulse period" \ -# "tooltip" "Period of the generated signal. The unit interval is the system or external clock period." \ -# ] [ipgui::get_guiparamspec -name "PULSE_PERIOD" -component $cc] -# ipx::create_xgui_files $cc -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:05 2021... diff --git a/adi_library/axi_pulse_gen/vivado.jou b/adi_library/axi_pulse_gen/vivado.jou deleted file mode 100644 index 3caaa755..00000000 --- a/adi_library/axi_pulse_gen/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:23:55 2021 -# Process ID: 145552 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen -# Command line: vivado -mode batch -source axi_pulse_gen_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen/vivado.jou -#----------------------------------------------------------- -source axi_pulse_gen_ip.tcl diff --git a/adi_library/axi_pulse_gen/vivado.log b/adi_library/axi_pulse_gen/vivado.log deleted file mode 100644 index 0201c850..00000000 --- a/adi_library/axi_pulse_gen/vivado.log +++ /dev/null @@ -1,769 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:23:55 2021 -# Process ID: 145552 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen -# Command line: vivado -mode batch -source axi_pulse_gen_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen/vivado.jou -#----------------------------------------------------------- -source axi_pulse_gen_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_pulse_gen -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_pulse_gen [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/common/util_pulse_gen.v" \ -# "axi_pulse_gen_constr.ttcl" \ -# "axi_pulse_gen_regmap.v" \ -# "axi_pulse_gen.v"] -# adi_ip_properties axi_pulse_gen -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen/axi_pulse_gen_constr.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ext_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3153] Bus Interface 'ext_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_ttcl axi_pulse_gen "axi_pulse_gen_constr.ttcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# } -# set cc [ipx::current_core] -# set_property display_name "ADI AXI Pulse Generator" $cc -# set_property description "ADI AXI Pulse Generator" $cc -# adi_add_bus ext_clk slave \ -# "xilinx.com:signal:clock_rtl:1.0" \ -# "xilinx.com:signal:clock:1.0" \ -# [list {"ext_clk" "CLK"} ] -# adi_set_ports_dependency "ext_clk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.ASYNC_CLK_EN')) = 1)" 0 -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "true" \ -# ] \ -# [ipx::get_user_parameters ASYNC_CLK_EN -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "true" \ -# ] \ -# [ipx::get_hdl_parameters ASYNC_CLK_EN -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "2147483647" \ -# ] \ -# [ipx::get_user_parameters PULSE_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "2147483647" \ -# ] \ -# [ipx::get_user_parameters PULSE_PERIOD -of_objects $cc] -# ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] -# ipx::save_core $cc -# ipgui::add_page -name {AXI Pulse Generator} -component $cc -display_name {AXI Pulse Generator} -# set page0 [ipgui::get_pagespec -name "AXI Pulse Generator" -component $cc] -# ipgui::add_param -name "ASYNC_CLK_EN" -component $cc -parent $page0 -# set_property -dict [list \ -# "display_name" "ASYNC_CLK_EN" \ -# "tooltip" "External clock for the counter" \ -# "widget" "checkBox" \ -# ] [ipgui::get_guiparamspec -name "ASYNC_CLK_EN" -component $cc] -# ipgui::add_param -name "PULSE_WIDTH" -component $cc -parent $page0 -# set_property -dict [list \ -# "display_name" "Pulse width" \ -# "tooltip" "Pulse width of the generated signal. The unit interval is the system or external clock period." \ -# ] [ipgui::get_guiparamspec -name "PULSE_WIDTH" -component $cc] -# ipgui::add_param -name "PULSE_PERIOD" -component $cc -parent $page0 -# set_property -dict [list \ -# "display_name" "Pulse period" \ -# "tooltip" "Period of the generated signal. The unit interval is the system or external clock period." \ -# ] [ipgui::get_guiparamspec -name "PULSE_PERIOD" -component $cc] -# ipx::create_xgui_files $cc -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:05 2021... diff --git a/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner_ip.log b/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner_ip.log deleted file mode 100644 index 3fd5f2ed..00000000 --- a/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner_ip.log +++ /dev/null @@ -1,1813 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_rd_wr_combiner_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_rd_wr_combiner -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_rd_wr_combiner'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_rd_wr_combiner [list \ -# "axi_rd_wr_combiner.v" \ -# ] -# adi_ip_properties_lite axi_rd_wr_combiner -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'm_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi_awaddr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 's_axi_awburst'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '3:0' is present in all ports of the interface 's_axi_awcache'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '3:0' is present in all ports of the interface 's_axi_awlen'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 's_axi_awprot'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 's_axi_awsize'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 's_axi_bresp'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_axi_wdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 's_axi_wstrb'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_rd_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_wr_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_32' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_33' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_34' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_35' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_36' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_37' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_38' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_39' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_40' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_41' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_42' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_43' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_44' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_45' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_46' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_47' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_48' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_49' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_50' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_51' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_52' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_53' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_54' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_55' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_56' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_57' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_58' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_59' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_60' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_61' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_62' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_63' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'm_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi_awaddr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 's_axi_awburst'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '3:0' is present in all ports of the interface 's_axi_awcache'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '3:0' is present in all ports of the interface 's_axi_awlen'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 's_axi_awprot'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 's_axi_awsize'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 's_axi_bresp'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_axi_wdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 's_axi_wstrb'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_rd_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_wr_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi_araddr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 's_axi_arburst'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '3:0' is present in all ports of the interface 's_axi_arcache'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '3:0' is present in all ports of the interface 's_axi_arlen'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 's_axi_arprot'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 's_axi_arsize'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_axi_rdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 's_axi_rresp'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_10' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_11' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_12' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_13' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_14' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_15' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_16' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_17' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_18' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_19' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_20' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_21' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_22' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_23' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_24' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_25' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_26' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_27' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_28' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_29' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_30' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_31' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_4' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_5' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_6' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_7' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_8' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_9' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_arburst_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_arburst_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_arcache_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_arcache_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axi'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_32': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_32': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_32': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_32': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_33': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_33': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_33': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_33': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_34': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_34': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_34': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_34': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_35': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_35': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_35': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_35': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_36': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_36': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_36': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_36': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_37': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_37': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_37': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_37': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_38': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_38': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_38': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_38': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_39': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_39': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_39': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_39': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_40': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_40': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_40': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_40': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_41': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_41': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_41': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_41': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_42': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_42': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_42': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_42': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_43': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_43': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_43': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_43': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_44': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_44': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_44': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_44': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_45': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_45': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_45': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_45': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_46': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_46': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_46': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_46': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_47': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_47': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_47': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_47': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_48': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_48': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_48': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_48': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_49': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_49': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_49': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_49': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_50': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_50': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_50': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_50': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_51': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_51': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_51': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_51': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_52': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_52': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_52': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_52': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_53': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_53': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_53': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_53': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_54': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_54': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_54': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_54': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_55': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_55': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_55': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_55': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_56': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_56': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_56': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_56': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_57': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_57': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_57': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_57': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_58': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_58': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_58': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_58': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_59': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_59': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_59': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_59': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_60': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_60': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_60': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_60': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_61': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_61': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_61': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_61': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_62': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_62': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_62': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_62': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_63': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_63': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_63': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_63': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_12': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_13': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_14': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_15': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_16': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_17': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_18': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_19': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_20': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_21': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_22': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_23': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_24': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_25': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_26': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_27': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_28': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_29': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_30': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_31': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arburst_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arburst_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arburst_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arburst_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arprot_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arprot_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arprot_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arprot_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arprot_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arprot_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_arready' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arready': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arready': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arsize_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arsize_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arsize_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arsize_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arsize_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arsize_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arvalid': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arvalid': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_12': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_13': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_14': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_15': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_16': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_17': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_18': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_19': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_20': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_21': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_22': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_23': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_24': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_25': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_26': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_27': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_28': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_29': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_30': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_31': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_32': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_32': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_33': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_33': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_34': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_34': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_35': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_35': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_36': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_36': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_37': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_37': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_38': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_38': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_39': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_39': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_40': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_40': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_41': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_41': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_42': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_42': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_43': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_43': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_44': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_44': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_45': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_45': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_46': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_46': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_47': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_47': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_48': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_48': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_49': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_49': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_50': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_50': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_51': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_51': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_52': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_52': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_53': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_53': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_54': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_54': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_55': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_55': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_56': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_56': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_57': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_57': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_58': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_58': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_59': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_59': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_60': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_60': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_61': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_61': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_62': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_62': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_63': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_63': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rlast' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rlast': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rlast': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rready': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rready': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rresp' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rresp_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rresp_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rresp' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rresp_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rresp_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rvalid' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rvalid': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rvalid': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_infer_mm_interfaces axi_rd_wr_combiner -INFO: [IP_Flow 19-3164] Bus Interface 'm_axi': References existing address space 'm_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axi'. -# adi_add_bus_clock "clk" "m_axi:s_wr_axi:s_rd_axi" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:16:26 2021... diff --git a/adi_library/axi_rd_wr_combiner/vivado.jou b/adi_library/axi_rd_wr_combiner/vivado.jou deleted file mode 100644 index 1e2ff2bc..00000000 --- a/adi_library/axi_rd_wr_combiner/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:16:19 2021 -# Process ID: 6214 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_rd_wr_combiner -# Command line: vivado -mode batch -source axi_rd_wr_combiner_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_rd_wr_combiner/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_rd_wr_combiner/vivado.jou -#----------------------------------------------------------- -source axi_rd_wr_combiner_ip.tcl diff --git a/adi_library/axi_rd_wr_combiner/vivado.log b/adi_library/axi_rd_wr_combiner/vivado.log deleted file mode 100644 index 9d9be44c..00000000 --- a/adi_library/axi_rd_wr_combiner/vivado.log +++ /dev/null @@ -1,1818 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:16:19 2021 -# Process ID: 6214 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_rd_wr_combiner -# Command line: vivado -mode batch -source axi_rd_wr_combiner_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_rd_wr_combiner/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_rd_wr_combiner/vivado.jou -#----------------------------------------------------------- -source axi_rd_wr_combiner_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_rd_wr_combiner -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_rd_wr_combiner'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_rd_wr_combiner [list \ -# "axi_rd_wr_combiner.v" \ -# ] -# adi_ip_properties_lite axi_rd_wr_combiner -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'm_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi_awaddr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 's_axi_awburst'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '3:0' is present in all ports of the interface 's_axi_awcache'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '3:0' is present in all ports of the interface 's_axi_awlen'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 's_axi_awprot'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 's_axi_awsize'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 's_axi_bresp'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_axi_wdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 's_axi_wstrb'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_rd_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_wr_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_32' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_33' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_34' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_35' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_36' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_37' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_38' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_39' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_40' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_41' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_42' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_43' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_44' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_45' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_46' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_47' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_48' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_49' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_50' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_51' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_52' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_53' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_54' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_55' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_56' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_57' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_58' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_59' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_60' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_61' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_62' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_63' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'm_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi_awaddr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 's_axi_awburst'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '3:0' is present in all ports of the interface 's_axi_awcache'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '3:0' is present in all ports of the interface 's_axi_awlen'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 's_axi_awprot'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 's_axi_awsize'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 's_axi_bresp'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_axi_wdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 's_axi_wstrb'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_rd_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_wr_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi_araddr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 's_axi_arburst'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '3:0' is present in all ports of the interface 's_axi_arcache'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '3:0' is present in all ports of the interface 's_axi_arlen'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 's_axi_arprot'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 's_axi_arsize'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_axi_rdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 's_axi_rresp'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_10' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_11' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_12' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_13' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_14' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_15' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_16' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_17' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_18' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_19' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_20' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_21' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_22' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_23' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_24' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_25' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_26' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_27' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_28' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_29' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_30' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_31' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_4' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_5' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_6' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_7' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_8' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_araddr_9' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_arburst_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_arburst_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_arcache_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_arcache_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axi'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_32': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_32': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_32': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_32': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_33': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_33': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_33': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_33': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_34': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_34': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_34': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_34': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_35': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_35': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_35': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_35': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_36': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_36': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_36': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_36': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_37': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_37': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_37': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_37': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_38': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_38': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_38': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_38': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_39': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_39': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_39': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_39': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_40': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_40': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_40': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_40': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_41': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_41': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_41': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_41': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_42': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_42': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_42': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_42': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_43': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_43': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_43': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_43': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_44': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_44': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_44': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_44': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_45': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_45': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_45': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_45': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_46': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_46': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_46': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_46': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_47': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_47': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_47': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_47': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_48': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_48': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_48': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_48': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_49': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_49': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_49': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_49': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_50': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_50': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_50': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_50': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_51': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_51': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_51': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_51': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_52': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_52': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_52': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_52': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_53': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_53': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_53': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_53': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_54': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_54': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_54': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_54': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_55': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_55': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_55': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_55': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_56': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_56': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_56': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_56': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_57': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_57': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_57': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_57': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_58': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_58': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_58': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_58': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_59': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_59': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_59': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_59': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_60': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_60': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_60': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_60': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_61': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_61': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_61': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_61': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_62': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_62': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_62': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_62': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_63': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_63': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_63': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_63': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_12': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_13': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_14': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_15': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_16': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_17': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_18': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_19': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_20': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_21': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_22': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_23': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_24': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_25': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_26': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_27': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_28': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_29': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_30': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_31': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_araddr_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arburst_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arburst_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arburst_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arburst_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arcache_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arlen_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arprot_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arprot_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arprot_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arprot_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arprot_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arprot_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_arready' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arready': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arready': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arsize_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arsize_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arsize_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arsize_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arsize_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arsize_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arvalid': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_arvalid': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_12': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_13': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_14': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_15': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_16': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_17': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_18': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_19': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_20': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_21': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_22': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_23': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_24': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_25': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_26': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_27': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_28': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_29': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_30': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_31': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_32': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_32': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_33': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_33': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_34': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_34': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_35': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_35': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_36': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_36': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_37': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_37': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_38': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_38': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_39': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_39': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_40': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_40': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_41': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_41': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_42': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_42': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_43': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_43': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_44': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_44': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_45': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_45': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_46': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_46': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_47': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_47': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_48': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_48': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_49': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_49': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_50': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_50': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_51': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_51': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_52': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_52': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_53': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_53': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_54': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_54': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_55': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_55': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_56': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_56': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_57': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_57': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_58': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_58': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_59': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_59': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_60': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_60': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_61': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_61': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_62': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_62': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_63': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_63': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rdata' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rdata_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rlast' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rlast': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rlast': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rready': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rready': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rresp' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rresp_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rresp_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rresp' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rresp_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rresp_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_rd_axi_rvalid' and definition port 'rd'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rvalid': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_rvalid': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_infer_mm_interfaces axi_rd_wr_combiner -INFO: [IP_Flow 19-3164] Bus Interface 'm_axi': References existing address space 'm_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axi'. -# adi_add_bus_clock "clk" "m_axi:s_wr_axi:s_rd_axi" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:16:26 2021... diff --git a/adi_library/axi_spdif_rx/axi_spdif_rx_ip.log b/adi_library/axi_spdif_rx/axi_spdif_rx_ip.log deleted file mode 100644 index f0f40272..00000000 --- a/adi_library/axi_spdif_rx/axi_spdif_rx_ip.log +++ /dev/null @@ -1,759 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_spdif_rx_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_spdif_rx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_spdif_rx [list \ -# "$ad_hdl_dir/library/common/axi_ctrlif.vhd" \ -# "$ad_hdl_dir/library/common/axi_streaming_dma_rx_fifo.vhd" \ -# "$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \ -# "$ad_hdl_dir/library/common/dma_fifo.vhd" \ -# "rx_phase_det.vhd" \ -# "rx_package.vhd" \ -# "rx_decode.vhd" \ -# "rx_status_reg.vhd" \ -# "axi_spdif_rx.vhd" ] -# adi_ip_properties axi_spdif_rx -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_rx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_rx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3157] Bus Interface 'dma_req_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'dma_req_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_req_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_infer_streaming_interfaces axi_spdif_rx -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'. -# adi_add_bus "dma_ack" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"dma_req_davalid" "TVALID"} \ -# {"dma_req_daready" "TREADY"} \ -# {"dma_req_datype" "TUSER"} ] -# adi_add_bus "dma_req" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"dma_req_drvalid" "TVALID"} \ -# {"dma_req_drready" "TREADY"} \ -# {"dma_req_drtype" "TUSER"} \ -# {"dma_req_drlast" "TLAST"} ] -# adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn" -# adi_set_bus_dependency "m_axis" "m_axis" \ -# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)" -# adi_set_bus_dependency "dma_ack" "dma_req_da" \ -# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" -# adi_set_bus_dependency "dma_req" "dma_req_dr" \ -# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" -# adi_set_ports_dependency "dma_req_aclk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" -# adi_set_ports_dependency "dma_req_rstn" \ -# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:16:38 2021... diff --git a/adi_library/axi_spdif_rx/vivado.jou b/adi_library/axi_spdif_rx/vivado.jou deleted file mode 100644 index 591d218c..00000000 --- a/adi_library/axi_spdif_rx/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:16:27 2021 -# Process ID: 6273 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx -# Command line: vivado -mode batch -source axi_spdif_rx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx/vivado.jou -#----------------------------------------------------------- -source axi_spdif_rx_ip.tcl diff --git a/adi_library/axi_spdif_rx/vivado.log b/adi_library/axi_spdif_rx/vivado.log deleted file mode 100644 index dd774b58..00000000 --- a/adi_library/axi_spdif_rx/vivado.log +++ /dev/null @@ -1,764 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:16:27 2021 -# Process ID: 6273 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx -# Command line: vivado -mode batch -source axi_spdif_rx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx/vivado.jou -#----------------------------------------------------------- -source axi_spdif_rx_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_spdif_rx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_spdif_rx [list \ -# "$ad_hdl_dir/library/common/axi_ctrlif.vhd" \ -# "$ad_hdl_dir/library/common/axi_streaming_dma_rx_fifo.vhd" \ -# "$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \ -# "$ad_hdl_dir/library/common/dma_fifo.vhd" \ -# "rx_phase_det.vhd" \ -# "rx_package.vhd" \ -# "rx_decode.vhd" \ -# "rx_status_reg.vhd" \ -# "axi_spdif_rx.vhd" ] -# adi_ip_properties axi_spdif_rx -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_rx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_rx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3157] Bus Interface 'dma_req_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'dma_req_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_req_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_infer_streaming_interfaces axi_spdif_rx -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'. -# adi_add_bus "dma_ack" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"dma_req_davalid" "TVALID"} \ -# {"dma_req_daready" "TREADY"} \ -# {"dma_req_datype" "TUSER"} ] -# adi_add_bus "dma_req" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"dma_req_drvalid" "TVALID"} \ -# {"dma_req_drready" "TREADY"} \ -# {"dma_req_drtype" "TUSER"} \ -# {"dma_req_drlast" "TLAST"} ] -# adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn" -# adi_set_bus_dependency "m_axis" "m_axis" \ -# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)" -# adi_set_bus_dependency "dma_ack" "dma_req_da" \ -# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" -# adi_set_bus_dependency "dma_req" "dma_req_dr" \ -# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" -# adi_set_ports_dependency "dma_req_aclk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" -# adi_set_ports_dependency "dma_req_rstn" \ -# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:16:38 2021... diff --git a/adi_library/axi_spdif_tx/axi_spdif_tx_ip.log b/adi_library/axi_spdif_tx/axi_spdif_tx_ip.log deleted file mode 100644 index 179296c1..00000000 --- a/adi_library/axi_spdif_tx/axi_spdif_tx_ip.log +++ /dev/null @@ -1,761 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_spdif_tx_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_spdif_tx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_spdif_tx [list \ -# "$ad_hdl_dir/library/common/axi_ctrlif.vhd" \ -# "$ad_hdl_dir/library/common/axi_streaming_dma_tx_fifo.vhd" \ -# "$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \ -# "$ad_hdl_dir/library/common/dma_fifo.vhd" \ -# "tx_package.vhd" \ -# "tx_encoder.vhd" \ -# "axi_spdif_tx.vhd" \ -# "axi_spdif_tx_constr.xdc" ] -# adi_ip_properties axi_spdif_tx -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_tx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_tx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'spdif_clk' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axis_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'spdif_clk': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3157] Bus Interface 'dma_req_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'dma_req_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_req_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3238] Range of address space is set to a full 4G (Address Block 'reg0' of Memory Map 's_axi'). Consider reducing this by setting the range of the address block to a lower number, or alternatively reduce the number of bits on the address line in your HDL's top level file interface. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_infer_streaming_interfaces axi_spdif_tx -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'spdif_data_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axis_aresetn'. -# adi_add_bus "dma_ack" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"dma_req_davalid" "TVALID"} \ -# {"dma_req_daready" "TREADY"} \ -# {"dma_req_datype" "TUSER"} ] -# adi_add_bus "dma_req" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"dma_req_drvalid" "TVALID"} \ -# {"dma_req_drready" "TREADY"} \ -# {"dma_req_drtype" "TUSER"} \ -# {"dma_req_drlast" "TLAST"} ] -# adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn" -# adi_set_bus_dependency "s_axis" "s_axis" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)" -# adi_set_bus_dependency "dma_ack" "dma_req_da" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" -# adi_set_bus_dependency "dma_req" "dma_req_dr" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" -# adi_set_ports_dependency "dma_req_aclk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" -# adi_set_ports_dependency "dma_req_rstn" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:23:28 2021... diff --git a/adi_library/axi_spdif_tx/vivado.jou b/adi_library/axi_spdif_tx/vivado.jou deleted file mode 100644 index e5a0ab2e..00000000 --- a/adi_library/axi_spdif_tx/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:23:17 2021 -# Process ID: 66771 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx -# Command line: vivado -mode batch -source axi_spdif_tx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx/vivado.jou -#----------------------------------------------------------- -source axi_spdif_tx_ip.tcl diff --git a/adi_library/axi_spdif_tx/vivado.log b/adi_library/axi_spdif_tx/vivado.log deleted file mode 100644 index 1c90a342..00000000 --- a/adi_library/axi_spdif_tx/vivado.log +++ /dev/null @@ -1,766 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:23:17 2021 -# Process ID: 66771 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx -# Command line: vivado -mode batch -source axi_spdif_tx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx/vivado.jou -#----------------------------------------------------------- -source axi_spdif_tx_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_spdif_tx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_spdif_tx [list \ -# "$ad_hdl_dir/library/common/axi_ctrlif.vhd" \ -# "$ad_hdl_dir/library/common/axi_streaming_dma_tx_fifo.vhd" \ -# "$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \ -# "$ad_hdl_dir/library/common/dma_fifo.vhd" \ -# "tx_package.vhd" \ -# "tx_encoder.vhd" \ -# "axi_spdif_tx.vhd" \ -# "axi_spdif_tx_constr.xdc" ] -# adi_ip_properties axi_spdif_tx -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_tx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_tx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'spdif_clk' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axis_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'spdif_clk': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3157] Bus Interface 'dma_req_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'dma_req_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_req_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3238] Range of address space is set to a full 4G (Address Block 'reg0' of Memory Map 's_axi'). Consider reducing this by setting the range of the address block to a lower number, or alternatively reduce the number of bits on the address line in your HDL's top level file interface. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_infer_streaming_interfaces axi_spdif_tx -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'spdif_data_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axis_aresetn'. -# adi_add_bus "dma_ack" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"dma_req_davalid" "TVALID"} \ -# {"dma_req_daready" "TREADY"} \ -# {"dma_req_datype" "TUSER"} ] -# adi_add_bus "dma_req" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"dma_req_drvalid" "TVALID"} \ -# {"dma_req_drready" "TREADY"} \ -# {"dma_req_drtype" "TUSER"} \ -# {"dma_req_drlast" "TLAST"} ] -# adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn" -# adi_set_bus_dependency "s_axis" "s_axis" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)" -# adi_set_bus_dependency "dma_ack" "dma_req_da" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" -# adi_set_bus_dependency "dma_req" "dma_req_dr" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" -# adi_set_ports_dependency "dma_req_aclk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" -# adi_set_ports_dependency "dma_req_rstn" \ -# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:23:28 2021... diff --git a/adi_library/axi_sysid/axi_sysid_ip.log b/adi_library/axi_sysid/axi_sysid_ip.log deleted file mode 100644 index 82cc278d..00000000 --- a/adi_library/axi_sysid/axi_sysid_ip.log +++ /dev/null @@ -1,708 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_sysid_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_sysid -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_sysid'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_sysid [list \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "axi_sysid.v"] -# adi_ip_properties axi_sysid -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_sysid'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_sysid'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '(ROM_WIDTH - 1):0' is present in all ports of the interface 'pr_rom'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(ROM_WIDTH - 1):0' is present in all ports of the interface 'sys_rom'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'pr_rom' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sys_rom' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(ROM_WIDTH - 1):0' is present in all ports of the interface 'pr_rom'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(ROM_WIDTH - 1):0' is present in all ports of the interface 'sys_rom'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'pr_rom': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sys_rom': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# set cc [ipx::current_core] -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:23:36 2021... diff --git a/adi_library/axi_sysid/vivado.jou b/adi_library/axi_sysid/vivado.jou deleted file mode 100644 index 78a7e6a2..00000000 --- a/adi_library/axi_sysid/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:23:28 2021 -# Process ID: 66837 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_sysid -# Command line: vivado -mode batch -source axi_sysid_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_sysid/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_sysid/vivado.jou -#----------------------------------------------------------- -source axi_sysid_ip.tcl diff --git a/adi_library/axi_sysid/vivado.log b/adi_library/axi_sysid/vivado.log deleted file mode 100644 index df954e1b..00000000 --- a/adi_library/axi_sysid/vivado.log +++ /dev/null @@ -1,713 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:23:28 2021 -# Process ID: 66837 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_sysid -# Command line: vivado -mode batch -source axi_sysid_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_sysid/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_sysid/vivado.jou -#----------------------------------------------------------- -source axi_sysid_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_sysid -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_sysid'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_sysid [list \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "axi_sysid.v"] -# adi_ip_properties axi_sysid -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_sysid'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_sysid'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '(ROM_WIDTH - 1):0' is present in all ports of the interface 'pr_rom'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(ROM_WIDTH - 1):0' is present in all ports of the interface 'sys_rom'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'pr_rom' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sys_rom' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(ROM_WIDTH - 1):0' is present in all ports of the interface 'pr_rom'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(ROM_WIDTH - 1):0' is present in all ports of the interface 'sys_rom'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'pr_rom': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sys_rom': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# set cc [ipx::current_core] -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:23:36 2021... diff --git a/adi_library/axi_usb_fx3/axi_usb_fx3_ip.log b/adi_library/axi_usb_fx3/axi_usb_fx3_ip.log deleted file mode 100644 index 286a68a8..00000000 --- a/adi_library/axi_usb_fx3/axi_usb_fx3_ip.log +++ /dev/null @@ -1,1050 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_usb_fx3_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_usb_fx3 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_usb_fx3 [list \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "axi_usb_fx3_core.v" \ -# "axi_usb_fx3_if.v" \ -# "axi_usb_fx3_reg.v" \ -# "axi_usb_fx3.v"] -# adi_ip_properties axi_usb_fx3 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'interface_fifo_wr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'interface_fifo_rd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_10' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_11' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_12' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_13' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_14' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_15' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_16' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_17' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_18' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_19' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_2' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_20' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_21' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_22' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_23' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_24' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_25' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_26' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_27' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_28' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_29' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_3' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_30' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_31' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_4' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_5' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_6' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_7' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_8' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_9' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_ilas_config' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port valid on bus interface abstraction jesd204_rx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_rx_ilas_config' of definition 'analog.com:interface:jesd204_rx_ilas_config:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'addr' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_0': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_1': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_10': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_11': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_12': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_13': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_14': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_15': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_16': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_17': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_18': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_19': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_2': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_20': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_21': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_22': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_23': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_24': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_25': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_26': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_27': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_28': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_29': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_3': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_30': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_31': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_4': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_5': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_6': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_7': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_8': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_9': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'addr' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_ilas_config': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'addr' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_rx_ilas_config': A port map to the required logical port "valid" of the bus abstraction "analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3158] Bus Interface 'm_axis': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. -WARNING: [IP_Flow 19-3158] Bus Interface 's_axis': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_infer_streaming_interfaces axi_usb_fx3 -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument). -INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'. -# ipx::associate_bus_interfaces -busif m_axis -clock s_axi_aclk [ipx::current_core] -# ipx::associate_bus_interfaces -busif s_axis -clock s_axi_aclk [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:16:48 2021... diff --git a/adi_library/axi_usb_fx3/vivado.jou b/adi_library/axi_usb_fx3/vivado.jou deleted file mode 100644 index 4578e52b..00000000 --- a/adi_library/axi_usb_fx3/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:16:39 2021 -# Process ID: 6356 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3 -# Command line: vivado -mode batch -source axi_usb_fx3_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3/vivado.jou -#----------------------------------------------------------- -source axi_usb_fx3_ip.tcl diff --git a/adi_library/axi_usb_fx3/vivado.log b/adi_library/axi_usb_fx3/vivado.log deleted file mode 100644 index 16a7484d..00000000 --- a/adi_library/axi_usb_fx3/vivado.log +++ /dev/null @@ -1,1055 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:16:39 2021 -# Process ID: 6356 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3 -# Command line: vivado -mode batch -source axi_usb_fx3_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3/vivado.jou -#----------------------------------------------------------- -source axi_usb_fx3_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_usb_fx3 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_usb_fx3 [list \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "axi_usb_fx3_core.v" \ -# "axi_usb_fx3_if.v" \ -# "axi_usb_fx3_reg.v" \ -# "axi_usb_fx3.v"] -# adi_ip_properties axi_usb_fx3 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'interface_fifo_wr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_wr_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'interface_fifo_rd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_10' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_11' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_12' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_13' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_14' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_15' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_16' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_17' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_18' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_19' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_2' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_20' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_21' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_22' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_23' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_24' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_25' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_26' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_27' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_28' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_29' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_3' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_30' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_31' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_4' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_5' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_6' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_7' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_8' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_fifo_rd_9' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_ilas_config' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port valid on bus interface abstraction jesd204_rx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_rx_ilas_config' of definition 'analog.com:interface:jesd204_rx_ilas_config:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_wr_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'addr' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_0': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_1': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_10': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_11': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_12': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_13': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_14': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_15': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_16': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_17': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_18': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_19': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_2': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_20': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_21': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_22': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_23': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_24': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_25': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_26': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_27': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_28': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_29': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_3': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_30': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_31': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_4': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_5': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_6': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_7': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_8': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_fifo_rd_9': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'addr' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_ilas_config': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'addr' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_rx_ilas_config': A port map to the required logical port "valid" of the bus abstraction "analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3158] Bus Interface 'm_axis': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. -WARNING: [IP_Flow 19-3158] Bus Interface 's_axis': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_infer_streaming_interfaces axi_usb_fx3 -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument). -INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'. -# ipx::associate_bus_interfaces -busif m_axis -clock s_axi_aclk [ipx::current_core] -# ipx::associate_bus_interfaces -busif s_axis -clock s_axi_aclk [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:16:48 2021... diff --git a/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.log b/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.log deleted file mode 100644 index 12af662b..00000000 --- a/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.log +++ /dev/null @@ -1,773 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source cn0363_dma_sequencer_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create cn0363_dma_sequencer -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_dma_sequencer'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files cn0363_dma_sequencer [list \ -# "cn0363_dma_sequencer.v" -# ] -# adi_ip_properties_lite cn0363_dma_sequencer -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dma_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data_filtered' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'i_q' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'i_q_filtered' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'phase' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dma_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'channel'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 'processing_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'processing_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data_filtered_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_filtered': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'i_q_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'i_q': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'i_q_filtered_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'i_q_filtered': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'phase_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'phase': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "phase" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"phase_valid" "TVALID"} \ -# {"phase_ready" "TREADY"} \ -# {"phase" "TDATA"} \ -# } -# adi_add_bus "data" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"data_valid" "TVALID"} \ -# {"data_ready" "TREADY"} \ -# {"data" "TDATA"} \ -# } -# adi_add_bus "data_filtered" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"data_filtered_valid" "TVALID"} \ -# {"data_filtered_ready" "TREADY"} \ -# {"data_filtered" "TDATA"} \ -# } -# adi_add_bus "i_q" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"i_q_valid" "TVALID"} \ -# {"i_q_ready" "TREADY"} \ -# {"i_q" "TDATA"} \ -# } -# adi_add_bus "i_q_filtered" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"i_q_filtered_valid" "TVALID"} \ -# {"i_q_filtered_ready" "TREADY"} \ -# {"i_q_filtered" "TDATA"} \ -# } -# adi_add_bus "dma_wr" "master" \ -# "analog.com:interface:fifo_wr_rtl:1.0" \ -# "analog.com:interface:fifo_wr:1.0" \ -# { -# {"dma_wr_en" "EN"} \ -# {"dma_wr_sync" "SYNC"} \ -# {"dma_wr_data" "DATA"} \ -# {"dma_wr_overflow" "OVERFLOW"} \ -# {"dma_wr_xfer_req" "XFER_REQ"} \ -# } -# adi_add_bus_clock "clk" "phase:data:data_filtered:i_q:i_q_filtered:dma_wr" "processing_resetn" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:16:56 2021... diff --git a/adi_library/cn0363/cn0363_dma_sequencer/vivado.jou b/adi_library/cn0363/cn0363_dma_sequencer/vivado.jou deleted file mode 100644 index de960e8d..00000000 --- a/adi_library/cn0363/cn0363_dma_sequencer/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:16:49 2021 -# Process ID: 6417 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_dma_sequencer -# Command line: vivado -mode batch -source cn0363_dma_sequencer_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_dma_sequencer/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_dma_sequencer/vivado.jou -#----------------------------------------------------------- -source cn0363_dma_sequencer_ip.tcl diff --git a/adi_library/cn0363/cn0363_dma_sequencer/vivado.log b/adi_library/cn0363/cn0363_dma_sequencer/vivado.log deleted file mode 100644 index 976eff03..00000000 --- a/adi_library/cn0363/cn0363_dma_sequencer/vivado.log +++ /dev/null @@ -1,778 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:16:49 2021 -# Process ID: 6417 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_dma_sequencer -# Command line: vivado -mode batch -source cn0363_dma_sequencer_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_dma_sequencer/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_dma_sequencer/vivado.jou -#----------------------------------------------------------- -source cn0363_dma_sequencer_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create cn0363_dma_sequencer -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_dma_sequencer'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files cn0363_dma_sequencer [list \ -# "cn0363_dma_sequencer.v" -# ] -# adi_ip_properties_lite cn0363_dma_sequencer -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dma_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data_filtered' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'i_q' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'i_q_filtered' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'phase' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'dma_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '13:0' is present in all ports of the interface 'channel'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 'processing_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'processing_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data_filtered_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_filtered': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'i_q_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'i_q': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'i_q_filtered_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'i_q_filtered': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'phase_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'phase': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "phase" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"phase_valid" "TVALID"} \ -# {"phase_ready" "TREADY"} \ -# {"phase" "TDATA"} \ -# } -# adi_add_bus "data" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"data_valid" "TVALID"} \ -# {"data_ready" "TREADY"} \ -# {"data" "TDATA"} \ -# } -# adi_add_bus "data_filtered" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"data_filtered_valid" "TVALID"} \ -# {"data_filtered_ready" "TREADY"} \ -# {"data_filtered" "TDATA"} \ -# } -# adi_add_bus "i_q" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"i_q_valid" "TVALID"} \ -# {"i_q_ready" "TREADY"} \ -# {"i_q" "TDATA"} \ -# } -# adi_add_bus "i_q_filtered" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"i_q_filtered_valid" "TVALID"} \ -# {"i_q_filtered_ready" "TREADY"} \ -# {"i_q_filtered" "TDATA"} \ -# } -# adi_add_bus "dma_wr" "master" \ -# "analog.com:interface:fifo_wr_rtl:1.0" \ -# "analog.com:interface:fifo_wr:1.0" \ -# { -# {"dma_wr_en" "EN"} \ -# {"dma_wr_sync" "SYNC"} \ -# {"dma_wr_data" "DATA"} \ -# {"dma_wr_overflow" "OVERFLOW"} \ -# {"dma_wr_xfer_req" "XFER_REQ"} \ -# } -# adi_add_bus_clock "clk" "phase:data:data_filtered:i_q:i_q_filtered:dma_wr" "processing_resetn" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:16:56 2021... diff --git a/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync_ip.log b/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync_ip.log deleted file mode 100644 index 499ab29b..00000000 --- a/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync_ip.log +++ /dev/null @@ -1,1108 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source cn0363_phase_data_sync_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create cn0363_phase_data_sync -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_phase_data_sync'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files cn0363_phase_data_sync [list \ -# "cn0363_phase_data_sync.v" -# ] -# adi_ip_properties_lite cn0363_phase_data_sync -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axis_phase'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '23:0' is present in all ports of the interface 'm_axis_sample'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 's_axis_sample'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_10' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_11' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_12' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_13' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_14' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_15' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_16' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_17' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_18' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_19' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_20' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_21' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_22' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_23' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_24' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_25' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_26' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_27' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_28' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_29' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_30' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_31' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_4' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_5' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_6' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_7' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_8' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_9' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_10' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_11' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_12' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_13' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_14' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_15' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_16' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_17' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_18' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_19' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_20' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_21' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_22' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_23' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_4' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_5' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_6' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_7' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_8' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_9' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_4' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_5' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_6' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_7' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'processing_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'processing_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_phase_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_sample_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_12': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_13': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_14': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_15': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_16': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_17': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_18': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_19': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_20': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_21': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_22': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_23': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_24': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_25': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_26': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_27': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_28': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_29': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_30': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_31': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_12': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_13': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_14': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_15': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_16': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_17': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_18': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_19': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_20': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_21': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_22': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_23': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "S_AXIS_SAMPLE" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"s_axis_sample_valid" "TVALID"} \ -# {"s_axis_sample_ready" "TREADY"} \ -# {"s_axis_sample_data" "TDATA"} \ -# } -# adi_add_bus "M_AXIS_SAMPLE" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"m_axis_sample_valid" "TVALID"} \ -# {"m_axis_sample_ready" "TREADY"} \ -# {"m_axis_sample_data" "TDATA"} \ -# } -# adi_add_bus "M_AXIS_PHASE" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"m_axis_phase_valid" "TVALID"} \ -# {"m_axis_phase_ready" "TREADY"} \ -# {"m_axis_phase_data" "TDATA"} \ -# } -# adi_add_bus_clock "clk" "S_AXIS_SAMPLE:M_AXIS_SAMPLE:M_AXIS_PHASE" "resetn" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:03 2021... diff --git a/adi_library/cn0363/cn0363_phase_data_sync/vivado.jou b/adi_library/cn0363/cn0363_phase_data_sync/vivado.jou deleted file mode 100644 index 59778429..00000000 --- a/adi_library/cn0363/cn0363_phase_data_sync/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:16:56 2021 -# Process ID: 6469 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_phase_data_sync -# Command line: vivado -mode batch -source cn0363_phase_data_sync_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_phase_data_sync/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_phase_data_sync/vivado.jou -#----------------------------------------------------------- -source cn0363_phase_data_sync_ip.tcl diff --git a/adi_library/cn0363/cn0363_phase_data_sync/vivado.log b/adi_library/cn0363/cn0363_phase_data_sync/vivado.log deleted file mode 100644 index ed526898..00000000 --- a/adi_library/cn0363/cn0363_phase_data_sync/vivado.log +++ /dev/null @@ -1,1113 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:16:56 2021 -# Process ID: 6469 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_phase_data_sync -# Command line: vivado -mode batch -source cn0363_phase_data_sync_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_phase_data_sync/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_phase_data_sync/vivado.jou -#----------------------------------------------------------- -source cn0363_phase_data_sync_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create cn0363_phase_data_sync -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cn0363/cn0363_phase_data_sync'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files cn0363_phase_data_sync [list \ -# "cn0363_phase_data_sync.v" -# ] -# adi_ip_properties_lite cn0363_phase_data_sync -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axis_phase'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '23:0' is present in all ports of the interface 'm_axis_sample'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 's_axis_sample'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_10' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_11' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_12' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_13' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_14' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_15' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_16' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_17' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_18' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_19' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_20' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_21' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_22' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_23' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_24' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_25' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_26' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_27' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_28' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_29' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_30' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_31' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_4' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_5' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_6' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_7' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_8' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_phase_9' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_10' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_11' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_12' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_13' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_14' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_15' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_16' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_17' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_18' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_19' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_20' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_21' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_22' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_23' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_4' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_5' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_6' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_7' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_8' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_sample_9' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_4' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_5' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_6' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_sample_7' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'processing_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'processing_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_phase_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_sample_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_12': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_13': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_14': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_15': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_16': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_17': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_18': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_19': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_20': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_21': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_22': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_23': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_24': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_25': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_26': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_27': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_28': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_29': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_30': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_31': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_phase_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_12': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_13': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_14': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_15': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_16': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_17': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_18': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_19': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_20': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_21': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_22': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_23': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_sample_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_sample_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_sample_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "S_AXIS_SAMPLE" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"s_axis_sample_valid" "TVALID"} \ -# {"s_axis_sample_ready" "TREADY"} \ -# {"s_axis_sample_data" "TDATA"} \ -# } -# adi_add_bus "M_AXIS_SAMPLE" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"m_axis_sample_valid" "TVALID"} \ -# {"m_axis_sample_ready" "TREADY"} \ -# {"m_axis_sample_data" "TDATA"} \ -# } -# adi_add_bus "M_AXIS_PHASE" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"m_axis_phase_valid" "TVALID"} \ -# {"m_axis_phase_ready" "TREADY"} \ -# {"m_axis_phase_data" "TDATA"} \ -# } -# adi_add_bus_clock "clk" "S_AXIS_SAMPLE:M_AXIS_SAMPLE:M_AXIS_PHASE" "resetn" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:03 2021... diff --git a/adi_library/cordic_demod/cordic_demod_ip.log b/adi_library/cordic_demod/cordic_demod_ip.log deleted file mode 100644 index 9c206078..00000000 --- a/adi_library/cordic_demod/cordic_demod_ip.log +++ /dev/null @@ -1,1233 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source cordic_demod_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create cordic_demod -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cordic_demod'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files cordic_demod [list \ -# "cordic_demod.v" \ -# ] -# adi_ip_properties_lite cordic_demod -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'm_axis'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_axis'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'm_axis'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_axis'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "S_AXIS" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"s_axis_valid" "TVALID"} \ -# {"s_axis_ready" "TREADY"} \ -# {"s_axis_data" "TDATA"} \ -# } -# adi_add_bus "M_AXIS" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"m_axis_valid" "TVALID"} \ -# {"m_axis_ready" "TREADY"} \ -# {"m_axis_data" "TDATA"} \ -# } -# adi_add_bus_clock "clk" "S_AXIS:M_AXIS" "resetn" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:11 2021... diff --git a/adi_library/cordic_demod/vivado.jou b/adi_library/cordic_demod/vivado.jou deleted file mode 100644 index db2fce17..00000000 --- a/adi_library/cordic_demod/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:17:04 2021 -# Process ID: 6524 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cordic_demod -# Command line: vivado -mode batch -source cordic_demod_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cordic_demod/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cordic_demod/vivado.jou -#----------------------------------------------------------- -source cordic_demod_ip.tcl diff --git a/adi_library/cordic_demod/vivado.log b/adi_library/cordic_demod/vivado.log deleted file mode 100644 index 1aa54872..00000000 --- a/adi_library/cordic_demod/vivado.log +++ /dev/null @@ -1,1238 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:17:04 2021 -# Process ID: 6524 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cordic_demod -# Command line: vivado -mode batch -source cordic_demod_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cordic_demod/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cordic_demod/vivado.jou -#----------------------------------------------------------- -source cordic_demod_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create cordic_demod -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/cordic_demod'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files cordic_demod [list \ -# "cordic_demod.v" \ -# ] -# adi_ip_properties_lite cordic_demod -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'm_axis'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_axis'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 'm_axis'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '63:0' is present in all ports of the interface 's_axis'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "S_AXIS" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"s_axis_valid" "TVALID"} \ -# {"s_axis_ready" "TREADY"} \ -# {"s_axis_data" "TDATA"} \ -# } -# adi_add_bus "M_AXIS" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"m_axis_valid" "TVALID"} \ -# {"m_axis_ready" "TREADY"} \ -# {"m_axis_data" "TDATA"} \ -# } -# adi_add_bus_clock "clk" "S_AXIS:M_AXIS" "resetn" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:11 2021... diff --git a/adi_library/interfaces/interfaces_ip.log b/adi_library/interfaces/interfaces_ip.log deleted file mode 100644 index ad29f865..00000000 --- a/adi_library/interfaces/interfaces_ip.log +++ /dev/null @@ -1,726 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source interfaces_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_if_define if_xcvr_cm -# adi_if_ports output 1 enb -# adi_if_ports output 12 addr -# adi_if_ports output 1 wr -# adi_if_ports output 16 wdata -# adi_if_ports input 16 rdata -# adi_if_ports input 1 ready -# adi_if_define if_xcvr_ch -# adi_if_ports input 1 pll_locked -# adi_if_ports output 1 rst -# adi_if_ports output 1 user_ready -# adi_if_ports input 1 rst_done -# adi_if_ports output 1 lpm_dfe_n -# adi_if_ports output 3 rate -# adi_if_ports output 2 sys_clk_sel -# adi_if_ports output 3 out_clk_sel -# adi_if_ports output 4 tx_diffctrl -# adi_if_ports output 5 tx_postcursor -# adi_if_ports output 5 tx_precursor -# adi_if_ports output 1 enb -# adi_if_ports output 12 addr -# adi_if_ports output 1 wr -# adi_if_ports output 16 wdata -# adi_if_ports input 16 rdata -# adi_if_ports input 1 ready -# adi_if_define if_gt_qpll -# adi_if_ports output 1 qpll_rst reset -# adi_if_ports output 1 qpll_ref_clk clock -# adi_if_define if_gt_pll -# adi_if_ports output 1 cpll_rst_m reset -# adi_if_ports output 1 cpll_ref_clk_in clock -# adi_if_define if_gt_rx -# adi_if_ports output 1 rx_p -# adi_if_ports output 1 rx_n -# adi_if_ports input 1 rx_rst reset -# adi_if_ports output 1 rx_rst_m reset -# adi_if_ports input 1 rx_pll_rst reset -# adi_if_ports input 1 rx_gt_rst reset -# adi_if_ports output 1 rx_gt_rst_m reset -# adi_if_ports input 1 rx_pll_locked -# adi_if_ports output 1 rx_pll_locked_m -# adi_if_ports input 1 rx_user_ready -# adi_if_ports output 1 rx_user_ready_m -# adi_if_ports input 1 rx_rst_done -# adi_if_ports output 1 rx_rst_done_m -# adi_if_ports input 1 rx_out_clk clock -# adi_if_ports output 1 rx_clk clock -# adi_if_ports output 1 rx_sysref -# adi_if_ports input 1 rx_sync -# adi_if_ports input 1 rx_sof -# adi_if_ports input 32 rx_data -# adi_if_ports input 1 rx_ip_rst reset -# adi_if_ports output 4 rx_ip_sof -# adi_if_ports output 32 rx_ip_data -# adi_if_ports input 1 rx_ip_sysref -# adi_if_ports output 1 rx_ip_sync -# adi_if_ports input 1 rx_ip_rst_done -# adi_if_define if_gt_tx -# adi_if_ports input 1 tx_p -# adi_if_ports input 1 tx_n -# adi_if_ports input 1 tx_rst reset -# adi_if_ports output 1 tx_rst_m reset -# adi_if_ports input 1 tx_pll_rst reset -# adi_if_ports input 1 tx_gt_rst reset -# adi_if_ports output 1 tx_gt_rst_m reset -# adi_if_ports input 1 tx_pll_locked -# adi_if_ports output 1 tx_pll_locked_m -# adi_if_ports input 1 tx_user_ready -# adi_if_ports output 1 tx_user_ready_m -# adi_if_ports input 1 tx_rst_done -# adi_if_ports output 1 tx_rst_done_m -# adi_if_ports input 1 tx_out_clk clock -# adi_if_ports output 1 tx_clk clock -# adi_if_ports output 1 tx_sysref -# adi_if_ports output 1 tx_sync -# adi_if_ports output 32 tx_data -# adi_if_ports input 1 tx_ip_rst reset -# adi_if_ports input 32 tx_ip_data -# adi_if_ports input 1 tx_ip_sysref -# adi_if_ports input 1 tx_ip_sync -# adi_if_ports input 1 tx_ip_rst_done -# adi_if_define if_gt_rx_ksig -# adi_if_ports output 4 rx_gt_ilas_f -# adi_if_ports output 4 rx_gt_ilas_q -# adi_if_ports output 4 rx_gt_ilas_a -# adi_if_ports output 4 rx_gt_ilas_r -# adi_if_ports output 4 rx_gt_cgs_k -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:25:23 2021... diff --git a/adi_library/interfaces/vivado.jou b/adi_library/interfaces/vivado.jou deleted file mode 100644 index 28b3a306..00000000 --- a/adi_library/interfaces/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:25:18 2021 -# Process ID: 146101 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/interfaces -# Command line: vivado -mode batch -source interfaces_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/interfaces/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/interfaces/vivado.jou -#----------------------------------------------------------- -source interfaces_ip.tcl diff --git a/adi_library/interfaces/vivado.log b/adi_library/interfaces/vivado.log deleted file mode 100644 index e95b53e1..00000000 --- a/adi_library/interfaces/vivado.log +++ /dev/null @@ -1,731 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:25:18 2021 -# Process ID: 146101 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/interfaces -# Command line: vivado -mode batch -source interfaces_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/interfaces/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/interfaces/vivado.jou -#----------------------------------------------------------- -source interfaces_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_if_define if_xcvr_cm -# adi_if_ports output 1 enb -# adi_if_ports output 12 addr -# adi_if_ports output 1 wr -# adi_if_ports output 16 wdata -# adi_if_ports input 16 rdata -# adi_if_ports input 1 ready -# adi_if_define if_xcvr_ch -# adi_if_ports input 1 pll_locked -# adi_if_ports output 1 rst -# adi_if_ports output 1 user_ready -# adi_if_ports input 1 rst_done -# adi_if_ports output 1 lpm_dfe_n -# adi_if_ports output 3 rate -# adi_if_ports output 2 sys_clk_sel -# adi_if_ports output 3 out_clk_sel -# adi_if_ports output 4 tx_diffctrl -# adi_if_ports output 5 tx_postcursor -# adi_if_ports output 5 tx_precursor -# adi_if_ports output 1 enb -# adi_if_ports output 12 addr -# adi_if_ports output 1 wr -# adi_if_ports output 16 wdata -# adi_if_ports input 16 rdata -# adi_if_ports input 1 ready -# adi_if_define if_gt_qpll -# adi_if_ports output 1 qpll_rst reset -# adi_if_ports output 1 qpll_ref_clk clock -# adi_if_define if_gt_pll -# adi_if_ports output 1 cpll_rst_m reset -# adi_if_ports output 1 cpll_ref_clk_in clock -# adi_if_define if_gt_rx -# adi_if_ports output 1 rx_p -# adi_if_ports output 1 rx_n -# adi_if_ports input 1 rx_rst reset -# adi_if_ports output 1 rx_rst_m reset -# adi_if_ports input 1 rx_pll_rst reset -# adi_if_ports input 1 rx_gt_rst reset -# adi_if_ports output 1 rx_gt_rst_m reset -# adi_if_ports input 1 rx_pll_locked -# adi_if_ports output 1 rx_pll_locked_m -# adi_if_ports input 1 rx_user_ready -# adi_if_ports output 1 rx_user_ready_m -# adi_if_ports input 1 rx_rst_done -# adi_if_ports output 1 rx_rst_done_m -# adi_if_ports input 1 rx_out_clk clock -# adi_if_ports output 1 rx_clk clock -# adi_if_ports output 1 rx_sysref -# adi_if_ports input 1 rx_sync -# adi_if_ports input 1 rx_sof -# adi_if_ports input 32 rx_data -# adi_if_ports input 1 rx_ip_rst reset -# adi_if_ports output 4 rx_ip_sof -# adi_if_ports output 32 rx_ip_data -# adi_if_ports input 1 rx_ip_sysref -# adi_if_ports output 1 rx_ip_sync -# adi_if_ports input 1 rx_ip_rst_done -# adi_if_define if_gt_tx -# adi_if_ports input 1 tx_p -# adi_if_ports input 1 tx_n -# adi_if_ports input 1 tx_rst reset -# adi_if_ports output 1 tx_rst_m reset -# adi_if_ports input 1 tx_pll_rst reset -# adi_if_ports input 1 tx_gt_rst reset -# adi_if_ports output 1 tx_gt_rst_m reset -# adi_if_ports input 1 tx_pll_locked -# adi_if_ports output 1 tx_pll_locked_m -# adi_if_ports input 1 tx_user_ready -# adi_if_ports output 1 tx_user_ready_m -# adi_if_ports input 1 tx_rst_done -# adi_if_ports output 1 tx_rst_done_m -# adi_if_ports input 1 tx_out_clk clock -# adi_if_ports output 1 tx_clk clock -# adi_if_ports output 1 tx_sysref -# adi_if_ports output 1 tx_sync -# adi_if_ports output 32 tx_data -# adi_if_ports input 1 tx_ip_rst reset -# adi_if_ports input 32 tx_ip_data -# adi_if_ports input 1 tx_ip_sysref -# adi_if_ports input 1 tx_ip_sync -# adi_if_ports input 1 tx_ip_rst_done -# adi_if_define if_gt_rx_ksig -# adi_if_ports output 4 rx_gt_ilas_f -# adi_if_ports output 4 rx_gt_ilas_q -# adi_if_ports output 4 rx_gt_ilas_a -# adi_if_ports output 4 rx_gt_ilas_r -# adi_if_ports output 4 rx_gt_cgs_k -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:25:23 2021... diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.log b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.log deleted file mode 100644 index e6918109..00000000 --- a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.log +++ /dev/null @@ -1,833 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source ad_ip_jesd204_tpl_adc_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create ad_ip_jesd204_tpl_adc -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files ad_ip_jesd204_tpl_adc [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "../ad_ip_jesd204_tpl_common/up_tpl_common.v" \ -# "ad_ip_jesd204_tpl_adc_core.v" \ -# "ad_ip_jesd204_tpl_adc_channel.v" \ -# "ad_ip_jesd204_tpl_adc_deframer.v" \ -# "ad_ip_jesd204_tpl_adc_pnmon.v" \ -# "ad_ip_jesd204_tpl_adc_regmap.v" \ -# "ad_ip_jesd204_tpl_adc.v" \ -# ] -# adi_ip_properties ad_ip_jesd204_tpl_adc -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '(((NUM_LANES * 8) * OCTETS_PER_BEAT) - 1):0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(((NUM_LANES * 8) * OCTETS_PER_BEAT) - 1):0' is present in all ports of the interface 'link'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'link' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(NUM_CHANNELS - 1):0' is present in all ports of the interface 'interface_spi_engine_offload_ctrl'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'link_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'link': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'link_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd ad_ip_jesd204_tpl_adc "bd/bd.tcl" -# set cc [ipx::current_core] -# set_property display_name "JESD204 Transport Layer for ADCs" $cc -# set_property description "JESD204 Transport Layer for ADCs" $cc -# adi_add_bus "link" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list \ -# {"link_ready" "TREADY"} \ -# {"link_valid" "TVALID"} \ -# {"link_data" "TDATA"} \ -# ] -# adi_add_bus_clock "link_clk" "link" -# foreach {p v} { -# "NUM_LANES" "1 2 3 4 8 16" \ -# "NUM_CHANNELS" "1 2 4 6 8 16 32 64" \ -# "BITS_PER_SAMPLE" "8 12 16" \ -# "CONVERTER_RESOLUTION" "8 11 12 16" \ -# "SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \ -# "OCTETS_PER_BEAT" "4 8" \ -# } { \ -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_list" $v \ -# ] [ipx::get_user_parameters $p -of_objects $cc] -# } -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration"] -# set p [ipgui::get_guiparamspec -name "ID" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $general_group -# set_property -dict [list \ -# "display_name" "Core ID" \ -# ] $p -# set framer_group [ipgui::add_group -name "JESD204 Deframer Configuration" -component $cc \ -# -parent $page0 -display_name "JESD204 Deframer Cofiguration"] -# set i 0 -# foreach {k v} { \ -# "NUM_LANES" "Number of Lanes (L)" \ -# "NUM_CHANNELS" "Number of Conveters (M)" \ -# "BITS_PER_SAMPLE" "Bits per Sample (N')" \ -# "CONVERTER_RESOLUTION" "Converter Resolution (N)" \ -# "SAMPLES_PER_FRAME" "Samples per Frame (S)" \ -# "OCTETS_PER_BEAT" "Octets per Beat" \ -# } { \ -# set p [ipgui::get_guiparamspec -name $k -component $cc] -# ipgui::move_param -component $cc -order $i $p -parent $framer_group -# set_property -dict [list \ -# WIDGET "comboBox" \ -# DISPLAY_NAME $v \ -# ] $p -# incr i -# } -# set datapath_group [ipgui::add_group -name "Datapath Configuration" -component $cc \ -# -parent $page0 -display_name "Datapath Cofiguration"] -# set i 0 -# foreach {k v w} { -# "TWOS_COMPLEMENT" "Use twos complement" "checkBox" \ -# } { \ -# set p [ipgui::get_guiparamspec -name $k -component $cc] -# ipgui::move_param -component $cc -order $i $p -parent $datapath_group -# set_property -dict [list \ -# WIDGET $w \ -# DISPLAY_NAME $v \ -# ] $p -# incr i -# } -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:32 2021... diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/vivado.jou b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/vivado.jou deleted file mode 100644 index 98dc7845..00000000 --- a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:24:15 2021 -# Process ID: 145684 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc -# Command line: vivado -mode batch -source ad_ip_jesd204_tpl_adc_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/vivado.jou -#----------------------------------------------------------- -source ad_ip_jesd204_tpl_adc_ip.tcl diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/vivado.log b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/vivado.log deleted file mode 100644 index 1403f315..00000000 --- a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/vivado.log +++ /dev/null @@ -1,838 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:24:15 2021 -# Process ID: 145684 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc -# Command line: vivado -mode batch -source ad_ip_jesd204_tpl_adc_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/vivado.jou -#----------------------------------------------------------- -source ad_ip_jesd204_tpl_adc_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create ad_ip_jesd204_tpl_adc -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files ad_ip_jesd204_tpl_adc [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/ad_datafmt.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_adc_common.v" \ -# "$ad_hdl_dir/library/common/up_adc_channel.v" \ -# "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "../ad_ip_jesd204_tpl_common/up_tpl_common.v" \ -# "ad_ip_jesd204_tpl_adc_core.v" \ -# "ad_ip_jesd204_tpl_adc_channel.v" \ -# "ad_ip_jesd204_tpl_adc_deframer.v" \ -# "ad_ip_jesd204_tpl_adc_pnmon.v" \ -# "ad_ip_jesd204_tpl_adc_regmap.v" \ -# "ad_ip_jesd204_tpl_adc.v" \ -# ] -# adi_ip_properties ad_ip_jesd204_tpl_adc -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '(((NUM_LANES * 8) * OCTETS_PER_BEAT) - 1):0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(((NUM_LANES * 8) * OCTETS_PER_BEAT) - 1):0' is present in all ports of the interface 'link'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'link' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(NUM_CHANNELS - 1):0' is present in all ports of the interface 'interface_spi_engine_offload_ctrl'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'link_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'link': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'link_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd ad_ip_jesd204_tpl_adc "bd/bd.tcl" -# set cc [ipx::current_core] -# set_property display_name "JESD204 Transport Layer for ADCs" $cc -# set_property description "JESD204 Transport Layer for ADCs" $cc -# adi_add_bus "link" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list \ -# {"link_ready" "TREADY"} \ -# {"link_valid" "TVALID"} \ -# {"link_data" "TDATA"} \ -# ] -# adi_add_bus_clock "link_clk" "link" -# foreach {p v} { -# "NUM_LANES" "1 2 3 4 8 16" \ -# "NUM_CHANNELS" "1 2 4 6 8 16 32 64" \ -# "BITS_PER_SAMPLE" "8 12 16" \ -# "CONVERTER_RESOLUTION" "8 11 12 16" \ -# "SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \ -# "OCTETS_PER_BEAT" "4 8" \ -# } { \ -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_list" $v \ -# ] [ipx::get_user_parameters $p -of_objects $cc] -# } -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration"] -# set p [ipgui::get_guiparamspec -name "ID" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $general_group -# set_property -dict [list \ -# "display_name" "Core ID" \ -# ] $p -# set framer_group [ipgui::add_group -name "JESD204 Deframer Configuration" -component $cc \ -# -parent $page0 -display_name "JESD204 Deframer Cofiguration"] -# set i 0 -# foreach {k v} { \ -# "NUM_LANES" "Number of Lanes (L)" \ -# "NUM_CHANNELS" "Number of Conveters (M)" \ -# "BITS_PER_SAMPLE" "Bits per Sample (N')" \ -# "CONVERTER_RESOLUTION" "Converter Resolution (N)" \ -# "SAMPLES_PER_FRAME" "Samples per Frame (S)" \ -# "OCTETS_PER_BEAT" "Octets per Beat" \ -# } { \ -# set p [ipgui::get_guiparamspec -name $k -component $cc] -# ipgui::move_param -component $cc -order $i $p -parent $framer_group -# set_property -dict [list \ -# WIDGET "comboBox" \ -# DISPLAY_NAME $v \ -# ] $p -# incr i -# } -# set datapath_group [ipgui::add_group -name "Datapath Configuration" -component $cc \ -# -parent $page0 -display_name "Datapath Cofiguration"] -# set i 0 -# foreach {k v w} { -# "TWOS_COMPLEMENT" "Use twos complement" "checkBox" \ -# } { \ -# set p [ipgui::get_guiparamspec -name $k -component $cc] -# ipgui::move_param -component $cc -order $i $p -parent $datapath_group -# set_property -dict [list \ -# WIDGET $w \ -# DISPLAY_NAME $v \ -# ] $p -# incr i -# } -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:32 2021... diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.log b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.log deleted file mode 100644 index b9790271..00000000 --- a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.log +++ /dev/null @@ -1,1161 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source ad_ip_jesd204_tpl_dac_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create ad_ip_jesd204_tpl_dac -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files ad_ip_jesd204_tpl_dac [list \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_iqcor.v" \ -# "$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "../ad_ip_jesd204_tpl_common/up_tpl_common.v" \ -# "ad_ip_jesd204_tpl_dac_channel.v" \ -# "ad_ip_jesd204_tpl_dac_core.v" \ -# "ad_ip_jesd204_tpl_dac_framer.v" \ -# "ad_ip_jesd204_tpl_dac_regmap.v" \ -# "ad_ip_jesd204_tpl_dac_pn.v" \ -# "ad_ip_jesd204_tpl_dac.v" ] -# adi_ip_properties ad_ip_jesd204_tpl_dac -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '(((NUM_LANES * 8) * OCTETS_PER_BEAT) - 1):0' is present in all ports of the interface 'link'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_in' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'link' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(NUM_CHANNELS - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(((NUM_LANES * 8) * OCTETS_PER_BEAT) - 1):0' is present in all ports of the interface 'link'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(NUM_CHANNELS - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(NUM_CHANNELS - 1):0' is present in all ports of the interface 'interface_spi_engine_offload_ctrl'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'link_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'link_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'link': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'link_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd ad_ip_jesd204_tpl_dac "bd/bd.tcl" -# set cc [ipx::current_core] -# set_property display_name "JESD204 Transport Layer for DACs" $cc -# set_property description "JESD204 Transport Layer for DACs" $cc -# adi_add_bus "link" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list \ -# {"link_ready" "TREADY"} \ -# {"link_valid" "TVALID"} \ -# {"link_data" "TDATA"} \ -# ] -# adi_add_bus_clock "link_clk" "link" -# set_property -dict [list \ -# "value_validation_type" "pairs" \ -# "value_validation_pairs" {"Polynominal" "0" "CORDIC" "1"} \ -# "enablement_tcl_expr" "\$DATAPATH_DISABLE == 0" \ -# ] [ipx::get_user_parameters DDS_TYPE -of_objects $cc] -# foreach p {DDS_CORDIC_DW DDS_CORDIC_PHASE_DW} { -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" 8 \ -# "value_validation_range_maximum" 20 \ -# "enablement_tcl_expr" "\$DATAPATH_DISABLE == 0 && \$DDS_TYPE == 1" \ -# ] [ipx::get_user_parameters $p -of_objects $cc] -# } -# foreach {p v} { -# "NUM_LANES" "1 2 3 4 8 16" \ -# "NUM_CHANNELS" "1 2 4 6 8 16 32 64" \ -# "BITS_PER_SAMPLE" "8 12 16" \ -# "CONVERTER_RESOLUTION" "8 11 12 16" \ -# "SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \ -# "OCTETS_PER_BEAT" "4 8" \ -# } { \ -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_list" $v \ -# ] [ipx::get_user_parameters $p -of_objects $cc] -# } -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration"] -# set p [ipgui::get_guiparamspec -name "ID" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $general_group -# set_property -dict [list \ -# "display_name" "Core ID" \ -# ] $p -# set framer_group [ipgui::add_group -name "JESD204 Framer Configuration" -component $cc \ -# -parent $page0 -display_name "JESD204 Framer Cofiguration"] -# set i 0 -# foreach {k v} { \ -# "NUM_LANES" "Number of Lanes (L)" \ -# "NUM_CHANNELS" "Number of Conveters (M)" \ -# "BITS_PER_SAMPLE" "Bits per Sample (N')" \ -# "CONVERTER_RESOLUTION" "Converter Resolution (N)" \ -# "SAMPLES_PER_FRAME" "Samples per Frame (S)" \ -# "OCTETS_PER_BEAT" "Octets per Beat" \ -# } { \ -# set p [ipgui::get_guiparamspec -name $k -component $cc] -# ipgui::move_param -component $cc -order $i $p -parent $framer_group -# set_property -dict [list \ -# WIDGET "comboBox" \ -# DISPLAY_NAME $v \ -# ] $p -# incr i -# } -# set datapath_group [ipgui::add_group -name "Datapath Configuration" -component $cc \ -# -parent $page0 -display_name "Datapath Cofiguration"] -# set i 0 -# foreach {k v w} { -# "DATAPATH_DISABLE" "Disable Datapath" "checkBox" \ -# "EXT_SYNC" "Enable external SYNC" "checkBox" \ -# "IQCORRECTION_DISABLE" "Disable IQ Correction" "checkBox" \ -# "DDS_TYPE" "DDS Type" "comboBox" \ -# "DDS_CORDIC_DW" "CORDIC DDS Data Width" "text" \ -# "DDS_CORDIC_PHASE_DW" "CORDIC DDS Phase Width" "text" \ -# } { \ -# set p [ipgui::get_guiparamspec -name $k -component $cc] -# ipgui::move_param -component $cc -order $i $p -parent $datapath_group -# set_property -dict [list \ -# WIDGET $w \ -# DISPLAY_NAME $v \ -# ] $p -# incr i -# } -WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified text.Providing a default widget -WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified text.Providing a default widget -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:08:56 2021... diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/vivado.jou b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/vivado.jou deleted file mode 100644 index 1a8ddca0..00000000 --- a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:08:36 2021 -# Process ID: 3609 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac -# Command line: vivado -mode batch -source ad_ip_jesd204_tpl_dac_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac/vivado.jou -#----------------------------------------------------------- -source ad_ip_jesd204_tpl_dac_ip.tcl diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/vivado.log b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/vivado.log deleted file mode 100644 index 95a262d0..00000000 --- a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/vivado.log +++ /dev/null @@ -1,1166 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:08:36 2021 -# Process ID: 3609 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac -# Command line: vivado -mode batch -source ad_ip_jesd204_tpl_dac_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac/vivado.jou -#----------------------------------------------------------- -source ad_ip_jesd204_tpl_dac_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create ad_ip_jesd204_tpl_dac -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files ad_ip_jesd204_tpl_dac [list \ -# "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine.v" \ -# "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ -# "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ -# "$ad_hdl_dir/library/common/ad_dds_2.v" \ -# "$ad_hdl_dir/library/common/ad_dds_1.v" \ -# "$ad_hdl_dir/library/common/ad_dds.v" \ -# "$ad_hdl_dir/library/common/ad_iqcor.v" \ -# "$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/up_clock_mon.v" \ -# "$ad_hdl_dir/library/common/up_dac_common.v" \ -# "$ad_hdl_dir/library/common/up_dac_channel.v" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ -# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ -# "../ad_ip_jesd204_tpl_common/up_tpl_common.v" \ -# "ad_ip_jesd204_tpl_dac_channel.v" \ -# "ad_ip_jesd204_tpl_dac_core.v" \ -# "ad_ip_jesd204_tpl_dac_framer.v" \ -# "ad_ip_jesd204_tpl_dac_regmap.v" \ -# "ad_ip_jesd204_tpl_dac_pn.v" \ -# "ad_ip_jesd204_tpl_dac.v" ] -# adi_ip_properties ad_ip_jesd204_tpl_dac -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_1.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_2.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_iqcor.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_dac_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '(((NUM_LANES * 8) * OCTETS_PER_BEAT) - 1):0' is present in all ports of the interface 'link'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_in' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'link' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(NUM_CHANNELS - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(((NUM_LANES * 8) * OCTETS_PER_BEAT) - 1):0' is present in all ports of the interface 'link'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(NUM_CHANNELS - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(NUM_CHANNELS - 1):0' is present in all ports of the interface 'interface_spi_engine_offload_ctrl'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'link_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'link_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'link': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'link_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_init_bd_tcl -# adi_ip_bd ad_ip_jesd204_tpl_dac "bd/bd.tcl" -# set cc [ipx::current_core] -# set_property display_name "JESD204 Transport Layer for DACs" $cc -# set_property description "JESD204 Transport Layer for DACs" $cc -# adi_add_bus "link" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list \ -# {"link_ready" "TREADY"} \ -# {"link_valid" "TVALID"} \ -# {"link_data" "TDATA"} \ -# ] -# adi_add_bus_clock "link_clk" "link" -# set_property -dict [list \ -# "value_validation_type" "pairs" \ -# "value_validation_pairs" {"Polynominal" "0" "CORDIC" "1"} \ -# "enablement_tcl_expr" "\$DATAPATH_DISABLE == 0" \ -# ] [ipx::get_user_parameters DDS_TYPE -of_objects $cc] -# foreach p {DDS_CORDIC_DW DDS_CORDIC_PHASE_DW} { -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" 8 \ -# "value_validation_range_maximum" 20 \ -# "enablement_tcl_expr" "\$DATAPATH_DISABLE == 0 && \$DDS_TYPE == 1" \ -# ] [ipx::get_user_parameters $p -of_objects $cc] -# } -# foreach {p v} { -# "NUM_LANES" "1 2 3 4 8 16" \ -# "NUM_CHANNELS" "1 2 4 6 8 16 32 64" \ -# "BITS_PER_SAMPLE" "8 12 16" \ -# "CONVERTER_RESOLUTION" "8 11 12 16" \ -# "SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \ -# "OCTETS_PER_BEAT" "4 8" \ -# } { \ -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_list" $v \ -# ] [ipx::get_user_parameters $p -of_objects $cc] -# } -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration"] -# set p [ipgui::get_guiparamspec -name "ID" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $general_group -# set_property -dict [list \ -# "display_name" "Core ID" \ -# ] $p -# set framer_group [ipgui::add_group -name "JESD204 Framer Configuration" -component $cc \ -# -parent $page0 -display_name "JESD204 Framer Cofiguration"] -# set i 0 -# foreach {k v} { \ -# "NUM_LANES" "Number of Lanes (L)" \ -# "NUM_CHANNELS" "Number of Conveters (M)" \ -# "BITS_PER_SAMPLE" "Bits per Sample (N')" \ -# "CONVERTER_RESOLUTION" "Converter Resolution (N)" \ -# "SAMPLES_PER_FRAME" "Samples per Frame (S)" \ -# "OCTETS_PER_BEAT" "Octets per Beat" \ -# } { \ -# set p [ipgui::get_guiparamspec -name $k -component $cc] -# ipgui::move_param -component $cc -order $i $p -parent $framer_group -# set_property -dict [list \ -# WIDGET "comboBox" \ -# DISPLAY_NAME $v \ -# ] $p -# incr i -# } -# set datapath_group [ipgui::add_group -name "Datapath Configuration" -component $cc \ -# -parent $page0 -display_name "Datapath Cofiguration"] -# set i 0 -# foreach {k v w} { -# "DATAPATH_DISABLE" "Disable Datapath" "checkBox" \ -# "EXT_SYNC" "Enable external SYNC" "checkBox" \ -# "IQCORRECTION_DISABLE" "Disable IQ Correction" "checkBox" \ -# "DDS_TYPE" "DDS Type" "comboBox" \ -# "DDS_CORDIC_DW" "CORDIC DDS Data Width" "text" \ -# "DDS_CORDIC_PHASE_DW" "CORDIC DDS Phase Width" "text" \ -# } { \ -# set p [ipgui::get_guiparamspec -name $k -component $cc] -# ipgui::move_param -component $cc -order $i $p -parent $datapath_group -# set_property -dict [list \ -# WIDGET $w \ -# DISPLAY_NAME $v \ -# ] $p -# incr i -# } -WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified text.Providing a default widget -WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified text.Providing a default widget -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:08:56 2021... diff --git a/adi_library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.log b/adi_library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.log deleted file mode 100644 index 014e1ed3..00000000 --- a/adi_library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.log +++ /dev/null @@ -1,706 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_jesd204_common_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_jesd204_common -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_common'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# add_files -fileset [get_filesets sources_1] [list \ -# "../../xilinx/common/up_clock_mon_constr.xdc" \ -# "../../common/up_clock_mon.v" \ -# "jesd204_up_common.v" \ -# "jesd204_up_sysref.v" \ -# ] -# adi_ip_properties_lite axi_jesd204_common -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_common'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_common'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_common'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'up'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ext_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'ext_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 'core_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'core_reset'. -INFO: [IP_Flow 19-4728] Bus Interface 'up_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'up_reset'. -WARNING: [IP_Flow 19-3153] Bus Interface 'core_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'up_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# } -# set_property display_name "ADI AXI JESD204B Common Library" [ipx::current_core] -# set_property description "ADI AXI JESD204B Common Library" [ipx::current_core] -# set_property hide_in_gui {1} [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:39 2021... diff --git a/adi_library/jesd204/axi_jesd204_common/vivado.jou b/adi_library/jesd204/axi_jesd204_common/vivado.jou deleted file mode 100644 index fa0b1748..00000000 --- a/adi_library/jesd204/axi_jesd204_common/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:24:33 2021 -# Process ID: 145783 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_common -# Command line: vivado -mode batch -source axi_jesd204_common_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_common/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_common/vivado.jou -#----------------------------------------------------------- -source axi_jesd204_common_ip.tcl diff --git a/adi_library/jesd204/axi_jesd204_common/vivado.log b/adi_library/jesd204/axi_jesd204_common/vivado.log deleted file mode 100644 index a8000776..00000000 --- a/adi_library/jesd204/axi_jesd204_common/vivado.log +++ /dev/null @@ -1,711 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:24:33 2021 -# Process ID: 145783 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_common -# Command line: vivado -mode batch -source axi_jesd204_common_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_common/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_common/vivado.jou -#----------------------------------------------------------- -source axi_jesd204_common_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_jesd204_common -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_common'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# add_files -fileset [get_filesets sources_1] [list \ -# "../../xilinx/common/up_clock_mon_constr.xdc" \ -# "../../common/up_clock_mon.v" \ -# "jesd204_up_common.v" \ -# "jesd204_up_sysref.v" \ -# ] -# adi_ip_properties_lite axi_jesd204_common -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_common'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_common'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_common'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'up'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ext_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'ext_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 'core_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'core_reset'. -INFO: [IP_Flow 19-4728] Bus Interface 'up_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'up_reset'. -WARNING: [IP_Flow 19-3153] Bus Interface 'core_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'up_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# } -# set_property display_name "ADI AXI JESD204B Common Library" [ipx::current_core] -# set_property description "ADI AXI JESD204B Common Library" [ipx::current_core] -# set_property hide_in_gui {1} [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:39 2021... diff --git a/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.log b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.log deleted file mode 100644 index 84f8dece..00000000 --- a/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.log +++ /dev/null @@ -1,840 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_jesd204_rx_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_jesd204_rx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_jesd204_rx [list \ -# "../../common/up_axi.v" \ -# "jesd204_up_rx.v" \ -# "jesd204_up_rx_lane.v" \ -# "jesd204_up_ilas_mem.v" \ -# "axi_jesd204_rx_constr.xdc" \ -# "axi_jesd204_rx_ooc.ttcl" \ -# "axi_jesd204_rx.v" \ -# ] -# adi_ip_properties axi_jesd204_rx -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'core_status_ctrl'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((2 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_status_lane_cgs'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((3 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_status_lane_emb'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_event_unexpected_lane_error' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_ctrl_0' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_ctrl_1' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_lane_cgs' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_lane_emb' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '((8 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_status_err_cnt'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port lane_frame_align on bus interface abstraction jesd204_rx_status_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port lane_latency_ready on bus interface abstraction jesd204_rx_status_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status' of definition 'analog.com:interface:jesd204_rx_status:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_event' of definition 'analog.com:interface:jesd204_tx_event:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_ctrl_err_statistics_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'core_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'core_ctrl_err_statistics_reset'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_lanes_disable' and definition port 'lanes_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_links_disable' and definition port 'links_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_beats_per_multiframe' and definition port 'beats_per_multiframe'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_octets_per_frame' and definition port 'octets_per_frame'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_lmfc_offset' and definition port 'lmfc_offset'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_buffer_early_release' and definition port 'buffer_early_release'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_buffer_delay' and definition port 'buffer_delay'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_disable_char_replacement' and definition port 'disable_char_replacement'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_disable_scrambler' and definition port 'disable_scrambler'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_frame_align_err_threshold' and definition port 'frame_align_err_threshold'. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_event_unexpected_lane_error': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_ctrl_0': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_ctrl_1': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_lane_cgs': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_lane_emb': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status': A port map to the required logical port "lane_frame_align" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status': A port map to the required logical port "lane_latency_ready" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'core_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_ttcl axi_jesd204_rx "axi_jesd204_rx_ooc.ttcl" -# set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_rx_constr.xdc \ -# -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \ -# -filter {NAME =~ *synthesis*}]] -# adi_ip_add_core_dependencies { \ -# analog.com:user:axi_jesd204_common:1.0 \ -# } -# set_property display_name "ADI JESD204C Receive AXI Interface" [ipx::current_core] -# set_property description "ADI JESD204C Receive AXI Interface" [ipx::current_core] -# adi_add_bus "rx_cfg" "master" \ -# "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_cfg:1.0" \ -# { \ -# { "core_cfg_lanes_disable" "lanes_disable" } \ -# { "core_cfg_links_disable" "links_disable" } \ -# { "core_cfg_beats_per_multiframe" "beats_per_multiframe" } \ -# { "core_cfg_octets_per_frame" "octets_per_frame" } \ -# { "core_cfg_lmfc_offset" "lmfc_offset" } \ -# { "core_cfg_sysref_oneshot" "sysref_oneshot" } \ -# { "core_cfg_sysref_disable" "sysref_disable" } \ -# { "core_ctrl_err_statistics_reset" "err_statistics_reset" } \ -# { "core_ctrl_err_statistics_mask" "err_statistics_mask" } \ -# { "core_cfg_buffer_early_release" "buffer_early_release" } \ -# { "core_cfg_buffer_delay" "buffer_delay" } \ -# { "core_cfg_disable_char_replacement" "disable_char_replacement" } \ -# { "core_cfg_disable_scrambler" "disable_scrambler" } \ -# { "core_cfg_frame_align_err_threshold" "frame_align_err_threshold" } \ -# } -# adi_add_bus "rx_ilas_config" "slave" \ -# "analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_ilas_config:1.0" \ -# { \ -# { "core_ilas_config_valid" "valid" } \ -# { "core_ilas_config_addr" "addr" } \ -# { "core_ilas_config_data" "data" } \ -# } -# adi_add_bus "rx_event" "slave" \ -# "analog.com:interface:jesd204_rx_event_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_event:1.0" \ -# { \ -# { "core_event_sysref_alignment_error" "sysref_alignment_error" } \ -# { "core_event_sysref_edge" "sysref_edge" } \ -# { "core_event_frame_alignment_error" "frame_alignment_error" } \ -# { "core_event_unexpected_lane_state_error" "unexpected_lane_state_error" } \ -# } -# adi_add_bus "rx_status" "slave" \ -# "analog.com:interface:jesd204_rx_status_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_status:1.0" \ -# { \ -# { "core_status_ctrl_state" "ctrl_state" } \ -# { "core_status_lane_cgs_state" "lane_cgs_state" } \ -# { "core_status_lane_emb_state" "lane_emb_state" } \ -# { "core_status_lane_ifs_ready" "lane_ifs_ready" } \ -# { "core_status_lane_latency" "lane_latency" } \ -# { "core_status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \ -# { "core_status_err_statistics_cnt" "err_statistics_cnt" } \ -# } -# ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -# adi_add_bus_clock "core_clk" "rx_status:rx_event:rx_ilas_config:rx_cfg" \ -# "core_reset" "master" -# set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"] -# adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# set cc [ipx::current_core] -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $page0 -# set_property -dict [list \ -# "display_name" "Link Layer mode" \ -# "tooltip" "Link Layer mode" \ -# "widget" "comboBox" \ -# ] $p -# set_property -dict [list \ -# value_validation_type pairs \ -# value_validation_pairs {64B66B 2 8B10B 1} \ -# ] [ipx::get_user_parameters $p -of_objects $cc] -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:55 2021... diff --git a/adi_library/jesd204/axi_jesd204_rx/vivado.jou b/adi_library/jesd204/axi_jesd204_rx/vivado.jou deleted file mode 100644 index 5946537c..00000000 --- a/adi_library/jesd204/axi_jesd204_rx/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:24:45 2021 -# Process ID: 145873 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx -# Command line: vivado -mode batch -source axi_jesd204_rx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx/vivado.jou -#----------------------------------------------------------- -source axi_jesd204_rx_ip.tcl diff --git a/adi_library/jesd204/axi_jesd204_rx/vivado.log b/adi_library/jesd204/axi_jesd204_rx/vivado.log deleted file mode 100644 index 5f2acd46..00000000 --- a/adi_library/jesd204/axi_jesd204_rx/vivado.log +++ /dev/null @@ -1,845 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:24:45 2021 -# Process ID: 145873 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx -# Command line: vivado -mode batch -source axi_jesd204_rx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx/vivado.jou -#----------------------------------------------------------- -source axi_jesd204_rx_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_jesd204_rx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_jesd204_rx [list \ -# "../../common/up_axi.v" \ -# "jesd204_up_rx.v" \ -# "jesd204_up_rx_lane.v" \ -# "jesd204_up_ilas_mem.v" \ -# "axi_jesd204_rx_constr.xdc" \ -# "axi_jesd204_rx_ooc.ttcl" \ -# "axi_jesd204_rx.v" \ -# ] -# adi_ip_properties axi_jesd204_rx -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'core_status_ctrl'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((2 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_status_lane_cgs'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((3 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_status_lane_emb'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_event_unexpected_lane_error' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_ctrl_0' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_ctrl_1' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_lane_cgs' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_lane_emb' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '((8 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_status_err_cnt'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port lane_frame_align on bus interface abstraction jesd204_rx_status_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port lane_latency_ready on bus interface abstraction jesd204_rx_status_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status' of definition 'analog.com:interface:jesd204_rx_status:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_event' of definition 'analog.com:interface:jesd204_tx_event:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_ctrl_err_statistics_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'core_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'core_ctrl_err_statistics_reset'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_lanes_disable' and definition port 'lanes_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_links_disable' and definition port 'links_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_beats_per_multiframe' and definition port 'beats_per_multiframe'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_octets_per_frame' and definition port 'octets_per_frame'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_lmfc_offset' and definition port 'lmfc_offset'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_buffer_early_release' and definition port 'buffer_early_release'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_buffer_delay' and definition port 'buffer_delay'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_disable_char_replacement' and definition port 'disable_char_replacement'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_disable_scrambler' and definition port 'disable_scrambler'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_frame_align_err_threshold' and definition port 'frame_align_err_threshold'. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_event_unexpected_lane_error': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_ctrl_0': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_ctrl_1': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_lane_cgs': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_lane_emb': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status': A port map to the required logical port "lane_frame_align" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status': A port map to the required logical port "lane_latency_ready" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'core_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_ttcl axi_jesd204_rx "axi_jesd204_rx_ooc.ttcl" -# set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_rx_constr.xdc \ -# -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \ -# -filter {NAME =~ *synthesis*}]] -# adi_ip_add_core_dependencies { \ -# analog.com:user:axi_jesd204_common:1.0 \ -# } -# set_property display_name "ADI JESD204C Receive AXI Interface" [ipx::current_core] -# set_property description "ADI JESD204C Receive AXI Interface" [ipx::current_core] -# adi_add_bus "rx_cfg" "master" \ -# "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_cfg:1.0" \ -# { \ -# { "core_cfg_lanes_disable" "lanes_disable" } \ -# { "core_cfg_links_disable" "links_disable" } \ -# { "core_cfg_beats_per_multiframe" "beats_per_multiframe" } \ -# { "core_cfg_octets_per_frame" "octets_per_frame" } \ -# { "core_cfg_lmfc_offset" "lmfc_offset" } \ -# { "core_cfg_sysref_oneshot" "sysref_oneshot" } \ -# { "core_cfg_sysref_disable" "sysref_disable" } \ -# { "core_ctrl_err_statistics_reset" "err_statistics_reset" } \ -# { "core_ctrl_err_statistics_mask" "err_statistics_mask" } \ -# { "core_cfg_buffer_early_release" "buffer_early_release" } \ -# { "core_cfg_buffer_delay" "buffer_delay" } \ -# { "core_cfg_disable_char_replacement" "disable_char_replacement" } \ -# { "core_cfg_disable_scrambler" "disable_scrambler" } \ -# { "core_cfg_frame_align_err_threshold" "frame_align_err_threshold" } \ -# } -# adi_add_bus "rx_ilas_config" "slave" \ -# "analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_ilas_config:1.0" \ -# { \ -# { "core_ilas_config_valid" "valid" } \ -# { "core_ilas_config_addr" "addr" } \ -# { "core_ilas_config_data" "data" } \ -# } -# adi_add_bus "rx_event" "slave" \ -# "analog.com:interface:jesd204_rx_event_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_event:1.0" \ -# { \ -# { "core_event_sysref_alignment_error" "sysref_alignment_error" } \ -# { "core_event_sysref_edge" "sysref_edge" } \ -# { "core_event_frame_alignment_error" "frame_alignment_error" } \ -# { "core_event_unexpected_lane_state_error" "unexpected_lane_state_error" } \ -# } -# adi_add_bus "rx_status" "slave" \ -# "analog.com:interface:jesd204_rx_status_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_status:1.0" \ -# { \ -# { "core_status_ctrl_state" "ctrl_state" } \ -# { "core_status_lane_cgs_state" "lane_cgs_state" } \ -# { "core_status_lane_emb_state" "lane_emb_state" } \ -# { "core_status_lane_ifs_ready" "lane_ifs_ready" } \ -# { "core_status_lane_latency" "lane_latency" } \ -# { "core_status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \ -# { "core_status_err_statistics_cnt" "err_statistics_cnt" } \ -# } -# ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -# adi_add_bus_clock "core_clk" "rx_status:rx_event:rx_ilas_config:rx_cfg" \ -# "core_reset" "master" -# set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"] -# adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# set cc [ipx::current_core] -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $page0 -# set_property -dict [list \ -# "display_name" "Link Layer mode" \ -# "tooltip" "Link Layer mode" \ -# "widget" "comboBox" \ -# ] $p -# set_property -dict [list \ -# value_validation_type pairs \ -# value_validation_pairs {64B66B 2 8B10B 1} \ -# ] [ipx::get_user_parameters $p -of_objects $cc] -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:55 2021... diff --git a/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.log b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.log deleted file mode 100644 index 2de28af4..00000000 --- a/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.log +++ /dev/null @@ -1,1122 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_jesd204_tx_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_jesd204_tx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_jesd204_tx [list \ -# "../../common/up_axi.v" \ -# "axi_jesd204_tx_constr.xdc" \ -# "axi_jesd204_tx_ooc.ttcl" \ -# "jesd204_up_tx.v" \ -# "axi_jesd204_tx.v" \ -# ] -# adi_ip_properties axi_jesd204_tx -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(NUM_LINKS - 1):0' is present in all ports of the interface 'core_status'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_ctrl_manual_request' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'core_ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'core_ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port buffer_early_release on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port buffer_delay on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port frame_align_err_threshold on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_event' of definition 'analog.com:interface:jesd204_tx_event:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_ctrl' of definition 'analog.com:interface:jesd204_tx_ctrl:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'core_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'core_reset'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_ctrl_manual_sync_request' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_ctrl_manual_request': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_ctrl_manual_request': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_ilas_config_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_lanes_disable' and definition port 'lanes_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_links_disable' and definition port 'links_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_beats_per_multiframe' and definition port 'beats_per_multiframe'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_octets_per_frame' and definition port 'octets_per_frame'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_lmfc_offset' and definition port 'lmfc_offset'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_disable_char_replacement' and definition port 'disable_char_replacement'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_disable_scrambler' and definition port 'disable_scrambler'. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "buffer_early_release" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "buffer_delay" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "frame_align_err_threshold" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'core_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_ttcl axi_jesd204_tx "axi_jesd204_tx_ooc.ttcl" -# set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_tx_constr.xdc \ -# -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \ -# -filter {NAME =~ *synthesis*}]] -# adi_ip_add_core_dependencies { \ -# analog.com:user:axi_jesd204_common:1.0 \ -# } -# set_property display_name "ADI JESD204C Transmit AXI Interface" [ipx::current_core] -# set_property description "ADI JESD204B Transmit AXI Interface" [ipx::current_core] -# adi_add_bus "tx_cfg" "master" \ -# "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_cfg:1.0" \ -# { \ -# { "core_cfg_lanes_disable" "lanes_disable" } \ -# { "core_cfg_links_disable" "links_disable" } \ -# { "core_cfg_beats_per_multiframe" "beats_per_multiframe" } \ -# { "core_cfg_octets_per_frame" "octets_per_frame" } \ -# { "core_cfg_lmfc_offset" "lmfc_offset" } \ -# { "core_cfg_sysref_oneshot" "sysref_oneshot" } \ -# { "core_cfg_sysref_disable" "sysref_disable" } \ -# { "core_cfg_continuous_cgs" "continuous_cgs" } \ -# { "core_cfg_continuous_ilas" "continuous_ilas" } \ -# { "core_cfg_skip_ilas" "skip_ilas" } \ -# { "core_cfg_mframes_per_ilas" "mframes_per_ilas" } \ -# { "core_cfg_disable_char_replacement" "disable_char_replacement" } \ -# { "core_cfg_disable_scrambler" "disable_scrambler" } \ -# } -# adi_add_bus "tx_ilas_config" "slave" \ -# "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_ilas_config:1.0" \ -# { \ -# { "core_ilas_config_rd" "rd" } \ -# { "core_ilas_config_addr" "addr" } \ -# { "core_ilas_config_data" "data" } \ -# } -# adi_add_bus "tx_event" "slave" \ -# "analog.com:interface:jesd204_tx_event_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_event:1.0" \ -# { \ -# { "core_event_sysref_alignment_error" "sysref_alignment_error" } \ -# { "core_event_sysref_edge" "sysref_edge" } \ -# } -# adi_add_bus "tx_status" "slave" \ -# "analog.com:interface:jesd204_tx_status_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_status:1.0" \ -# { \ -# { "core_status_state" "state" } \ -# { "core_status_sync" "sync" } \ -# } -# adi_add_bus "tx_ctrl" "master" \ -# "analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_ctrl:1.0" \ -# { \ -# { "core_ctrl_manual_sync_request" "manual_sync_request" } \ -# } -# ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -# adi_add_bus_clock "core_clk" "tx_status:tx_event:tx_ilas_config:tx_cfg:tx_ctrl" \ -# "core_reset" "master" -# set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"] -# adi_set_bus_dependency "tx_ilas_config" "tx_ilas_config" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# adi_set_bus_dependency "tx_ctrl" "tx_ctrl" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# set cc [ipx::current_core] -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $page0 -# set_property -dict [list \ -# "display_name" "Link Layer mode" \ -# "tooltip" "Link Layer mode" \ -# "widget" "comboBox" \ -# ] $p -# set_property -dict [list \ -# value_validation_type pairs \ -# value_validation_pairs {64B66B 2 8B10B 1} \ -# ] [ipx::get_user_parameters $p -of_objects $cc] -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:20 2021... diff --git a/adi_library/jesd204/axi_jesd204_tx/vivado.jou b/adi_library/jesd204/axi_jesd204_tx/vivado.jou deleted file mode 100644 index c6542ba1..00000000 --- a/adi_library/jesd204/axi_jesd204_tx/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:17:11 2021 -# Process ID: 6698 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx -# Command line: vivado -mode batch -source axi_jesd204_tx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx/vivado.jou -#----------------------------------------------------------- -source axi_jesd204_tx_ip.tcl diff --git a/adi_library/jesd204/axi_jesd204_tx/vivado.log b/adi_library/jesd204/axi_jesd204_tx/vivado.log deleted file mode 100644 index 952b4f8b..00000000 --- a/adi_library/jesd204/axi_jesd204_tx/vivado.log +++ /dev/null @@ -1,1127 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:17:11 2021 -# Process ID: 6698 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx -# Command line: vivado -mode batch -source axi_jesd204_tx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx/vivado.jou -#----------------------------------------------------------- -source axi_jesd204_tx_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_jesd204_tx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_jesd204_tx [list \ -# "../../common/up_axi.v" \ -# "axi_jesd204_tx_constr.xdc" \ -# "axi_jesd204_tx_ooc.ttcl" \ -# "jesd204_up_tx.v" \ -# "axi_jesd204_tx.v" \ -# ] -# adi_ip_properties axi_jesd204_tx -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(NUM_LINKS - 1):0' is present in all ports of the interface 'core_status'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_ctrl_manual_request' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'core_ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'core_ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port buffer_early_release on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port buffer_delay on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port frame_align_err_threshold on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_event' of definition 'analog.com:interface:jesd204_tx_event:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_ctrl' of definition 'analog.com:interface:jesd204_tx_ctrl:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'core_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 'core_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'core_reset'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_ctrl_manual_sync_request' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_ctrl_manual_request': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_ctrl_manual_request': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_ilas_config_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_status': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_lanes_disable' and definition port 'lanes_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_links_disable' and definition port 'links_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_beats_per_multiframe' and definition port 'beats_per_multiframe'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_octets_per_frame' and definition port 'octets_per_frame'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_lmfc_offset' and definition port 'lmfc_offset'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_disable_char_replacement' and definition port 'disable_char_replacement'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_disable_scrambler' and definition port 'disable_scrambler'. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "buffer_early_release" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "buffer_delay" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "frame_align_err_threshold" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'core_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_ttcl axi_jesd204_tx "axi_jesd204_tx_ooc.ttcl" -# set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_tx_constr.xdc \ -# -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \ -# -filter {NAME =~ *synthesis*}]] -# adi_ip_add_core_dependencies { \ -# analog.com:user:axi_jesd204_common:1.0 \ -# } -# set_property display_name "ADI JESD204C Transmit AXI Interface" [ipx::current_core] -# set_property description "ADI JESD204B Transmit AXI Interface" [ipx::current_core] -# adi_add_bus "tx_cfg" "master" \ -# "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_cfg:1.0" \ -# { \ -# { "core_cfg_lanes_disable" "lanes_disable" } \ -# { "core_cfg_links_disable" "links_disable" } \ -# { "core_cfg_beats_per_multiframe" "beats_per_multiframe" } \ -# { "core_cfg_octets_per_frame" "octets_per_frame" } \ -# { "core_cfg_lmfc_offset" "lmfc_offset" } \ -# { "core_cfg_sysref_oneshot" "sysref_oneshot" } \ -# { "core_cfg_sysref_disable" "sysref_disable" } \ -# { "core_cfg_continuous_cgs" "continuous_cgs" } \ -# { "core_cfg_continuous_ilas" "continuous_ilas" } \ -# { "core_cfg_skip_ilas" "skip_ilas" } \ -# { "core_cfg_mframes_per_ilas" "mframes_per_ilas" } \ -# { "core_cfg_disable_char_replacement" "disable_char_replacement" } \ -# { "core_cfg_disable_scrambler" "disable_scrambler" } \ -# } -# adi_add_bus "tx_ilas_config" "slave" \ -# "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_ilas_config:1.0" \ -# { \ -# { "core_ilas_config_rd" "rd" } \ -# { "core_ilas_config_addr" "addr" } \ -# { "core_ilas_config_data" "data" } \ -# } -# adi_add_bus "tx_event" "slave" \ -# "analog.com:interface:jesd204_tx_event_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_event:1.0" \ -# { \ -# { "core_event_sysref_alignment_error" "sysref_alignment_error" } \ -# { "core_event_sysref_edge" "sysref_edge" } \ -# } -# adi_add_bus "tx_status" "slave" \ -# "analog.com:interface:jesd204_tx_status_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_status:1.0" \ -# { \ -# { "core_status_state" "state" } \ -# { "core_status_sync" "sync" } \ -# } -# adi_add_bus "tx_ctrl" "master" \ -# "analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_ctrl:1.0" \ -# { \ -# { "core_ctrl_manual_sync_request" "manual_sync_request" } \ -# } -# ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -# adi_add_bus_clock "core_clk" "tx_status:tx_event:tx_ilas_config:tx_cfg:tx_ctrl" \ -# "core_reset" "master" -# set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"] -# adi_set_bus_dependency "tx_ilas_config" "tx_ilas_config" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# adi_set_bus_dependency "tx_ctrl" "tx_ctrl" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# set cc [ipx::current_core] -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $page0 -# set_property -dict [list \ -# "display_name" "Link Layer mode" \ -# "tooltip" "Link Layer mode" \ -# "widget" "comboBox" \ -# ] $p -# set_property -dict [list \ -# value_validation_type pairs \ -# value_validation_pairs {64B66B 2 8B10B 1} \ -# ] [ipx::get_user_parameters $p -of_objects $cc] -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:20 2021... diff --git a/adi_library/jesd204/interfaces/interfaces_ip.log b/adi_library/jesd204/interfaces/interfaces_ip.log deleted file mode 100644 index db681a03..00000000 --- a/adi_library/jesd204/interfaces/interfaces_ip.log +++ /dev/null @@ -1,694 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source interfaces_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_if_define "jesd204_tx_cfg" -# adi_if_ports output -1 lanes_disable -# adi_if_ports output -1 links_disable -# adi_if_ports output 8 beats_per_multiframe -# adi_if_ports output 8 octets_per_frame -# adi_if_ports output 8 lmfc_offset -# adi_if_ports output 1 continuous_cgs -# adi_if_ports output 1 continuous_ilas -# adi_if_ports output 1 skip_ilas -# adi_if_ports output 8 mframes_per_ilas -# adi_if_ports output 1 disable_char_replacement -# adi_if_ports output 1 disable_scrambler -# adi_if_define "jesd204_tx_ilas_config" -# adi_if_ports output 1 rd -# adi_if_ports output 2 addr -# adi_if_ports input 32 data -# adi_if_define "jesd204_tx_status" -# adi_if_ports output 1 state -# adi_if_ports output 1 sync -# adi_if_define "jesd204_tx_event" -# adi_if_ports output 1 sysref_alignment_error -# adi_if_ports output 1 sysref_edge -# adi_if_define "jesd204_tx_ctrl" -# adi_if_ports output 1 manual_sync_request -# adi_if_define "jesd204_rx_cfg" -# adi_if_ports output -1 lanes_disable -# adi_if_ports output -1 links_disable -# adi_if_ports output 8 beats_per_multiframe -# adi_if_ports output 8 octets_per_frame -# adi_if_ports output 8 lmfc_offset -# adi_if_ports output 1 buffer_early_release -# adi_if_ports output 1 buffer_delay -# adi_if_ports output 1 disable_char_replacement -# adi_if_ports output 1 disable_scrambler -# adi_if_ports output 8 frame_align_err_threshold -# adi_if_ports output 1 err_statistics_reset -# adi_if_ports output 7 err_statistics_mask -# adi_if_define "jesd204_rx_status" -# adi_if_ports output 3 ctrl_state -# adi_if_ports output -1 lane_cgs_state -# adi_if_ports output -1 lane_emb_state -# adi_if_ports output -1 lane_frame_align -# adi_if_ports output -1 lane_ifs_ready -# adi_if_ports output -1 lane_latency_ready -# adi_if_ports output -1 lane_latency -# adi_if_ports output -1 err_statistics_cnt -# adi_if_define "jesd204_rx_ilas_config" -# adi_if_ports output -1 valid -# adi_if_ports output -1 addr -# adi_if_ports input -1 data -# adi_if_define "jesd204_rx_event" -# adi_if_ports output 1 sysref_alignment_error -# adi_if_ports output 1 sysref_edge -# adi_if_ports output 1 frame_alignment_error -# adi_if_ports output 1 unexpected_lane_state_error -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:45 2021... diff --git a/adi_library/jesd204/interfaces/vivado.jou b/adi_library/jesd204/interfaces/vivado.jou deleted file mode 100644 index 39929cfe..00000000 --- a/adi_library/jesd204/interfaces/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:24:40 2021 -# Process ID: 145830 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/interfaces -# Command line: vivado -mode batch -source interfaces_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/interfaces/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/interfaces/vivado.jou -#----------------------------------------------------------- -source interfaces_ip.tcl diff --git a/adi_library/jesd204/interfaces/vivado.log b/adi_library/jesd204/interfaces/vivado.log deleted file mode 100644 index bdbc838e..00000000 --- a/adi_library/jesd204/interfaces/vivado.log +++ /dev/null @@ -1,699 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:24:40 2021 -# Process ID: 145830 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/interfaces -# Command line: vivado -mode batch -source interfaces_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/interfaces/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/interfaces/vivado.jou -#----------------------------------------------------------- -source interfaces_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_if_define "jesd204_tx_cfg" -# adi_if_ports output -1 lanes_disable -# adi_if_ports output -1 links_disable -# adi_if_ports output 8 beats_per_multiframe -# adi_if_ports output 8 octets_per_frame -# adi_if_ports output 8 lmfc_offset -# adi_if_ports output 1 continuous_cgs -# adi_if_ports output 1 continuous_ilas -# adi_if_ports output 1 skip_ilas -# adi_if_ports output 8 mframes_per_ilas -# adi_if_ports output 1 disable_char_replacement -# adi_if_ports output 1 disable_scrambler -# adi_if_define "jesd204_tx_ilas_config" -# adi_if_ports output 1 rd -# adi_if_ports output 2 addr -# adi_if_ports input 32 data -# adi_if_define "jesd204_tx_status" -# adi_if_ports output 1 state -# adi_if_ports output 1 sync -# adi_if_define "jesd204_tx_event" -# adi_if_ports output 1 sysref_alignment_error -# adi_if_ports output 1 sysref_edge -# adi_if_define "jesd204_tx_ctrl" -# adi_if_ports output 1 manual_sync_request -# adi_if_define "jesd204_rx_cfg" -# adi_if_ports output -1 lanes_disable -# adi_if_ports output -1 links_disable -# adi_if_ports output 8 beats_per_multiframe -# adi_if_ports output 8 octets_per_frame -# adi_if_ports output 8 lmfc_offset -# adi_if_ports output 1 buffer_early_release -# adi_if_ports output 1 buffer_delay -# adi_if_ports output 1 disable_char_replacement -# adi_if_ports output 1 disable_scrambler -# adi_if_ports output 8 frame_align_err_threshold -# adi_if_ports output 1 err_statistics_reset -# adi_if_ports output 7 err_statistics_mask -# adi_if_define "jesd204_rx_status" -# adi_if_ports output 3 ctrl_state -# adi_if_ports output -1 lane_cgs_state -# adi_if_ports output -1 lane_emb_state -# adi_if_ports output -1 lane_frame_align -# adi_if_ports output -1 lane_ifs_ready -# adi_if_ports output -1 lane_latency_ready -# adi_if_ports output -1 lane_latency -# adi_if_ports output -1 err_statistics_cnt -# adi_if_define "jesd204_rx_ilas_config" -# adi_if_ports output -1 valid -# adi_if_ports output -1 addr -# adi_if_ports input -1 data -# adi_if_define "jesd204_rx_event" -# adi_if_ports output 1 sysref_alignment_error -# adi_if_ports output 1 sysref_edge -# adi_if_ports output 1 frame_alignment_error -# adi_if_ports output 1 unexpected_lane_state_error -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:45 2021... diff --git a/adi_library/jesd204/jesd204_common/jesd204_common_ip.log b/adi_library/jesd204/jesd204_common/jesd204_common_ip.log deleted file mode 100644 index ee312bc7..00000000 --- a/adi_library/jesd204/jesd204_common/jesd204_common_ip.log +++ /dev/null @@ -1,693 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source jesd204_common_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create jesd204_common -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_common'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# add_files -fileset [get_filesets sources_1] [list \ -# "jesd204_lmfc.v" \ -# "jesd204_scrambler.v" \ -# "jesd204_scrambler_64b.v" \ -# "jesd204_crc12.v" \ -# "jesd204_eof_generator.v" \ -# "pipeline_stage.v" \ -# ] -# adi_ip_properties_lite jesd204_common -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# set_property display_name "ADI JESD204C Common Library" [ipx::current_core] -# set_property description "ADI JESD204C Common Library" [ipx::current_core] -# set_property hide_in_gui {1} [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:25:02 2021... diff --git a/adi_library/jesd204/jesd204_common/vivado.jou b/adi_library/jesd204/jesd204_common/vivado.jou deleted file mode 100644 index 98627f50..00000000 --- a/adi_library/jesd204/jesd204_common/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:24:56 2021 -# Process ID: 145941 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_common -# Command line: vivado -mode batch -source jesd204_common_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_common/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_common/vivado.jou -#----------------------------------------------------------- -source jesd204_common_ip.tcl diff --git a/adi_library/jesd204/jesd204_common/vivado.log b/adi_library/jesd204/jesd204_common/vivado.log deleted file mode 100644 index 459427ca..00000000 --- a/adi_library/jesd204/jesd204_common/vivado.log +++ /dev/null @@ -1,698 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:24:56 2021 -# Process ID: 145941 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_common -# Command line: vivado -mode batch -source jesd204_common_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_common/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_common/vivado.jou -#----------------------------------------------------------- -source jesd204_common_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create jesd204_common -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_common'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# add_files -fileset [get_filesets sources_1] [list \ -# "jesd204_lmfc.v" \ -# "jesd204_scrambler.v" \ -# "jesd204_scrambler_64b.v" \ -# "jesd204_crc12.v" \ -# "jesd204_eof_generator.v" \ -# "pipeline_stage.v" \ -# ] -# adi_ip_properties_lite jesd204_common -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# set_property display_name "ADI JESD204C Common Library" [ipx::current_core] -# set_property description "ADI JESD204C Common Library" [ipx::current_core] -# set_property hide_in_gui {1} [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:25:02 2021... diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx_ip.log b/adi_library/jesd204/jesd204_rx/jesd204_rx_ip.log deleted file mode 100644 index fa64bf7c..00000000 --- a/adi_library/jesd204/jesd204_rx/jesd204_rx_ip.log +++ /dev/null @@ -1,870 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source jesd204_rx_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create jesd204_rx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files jesd204_rx [list \ -# "jesd204_rx_lane.v" \ -# "jesd204_rx_lane_64b.v" \ -# "jesd204_rx_header.v" \ -# "jesd204_rx_cgs.v" \ -# "jesd204_rx_ctrl.v" \ -# "jesd204_rx_ctrl_64b.v" \ -# "elastic_buffer.v" \ -# "error_monitor.v" \ -# "jesd204_ilas_monitor.v" \ -# "align_mux.v" \ -# "jesd204_lane_latency_monitor.v" \ -# "jesd204_rx_frame_mark.v" \ -# "jesd204_rx_frame_align_monitor.v" \ -# "jesd204_rx_constr.ttcl" \ -# "jesd204_rx.v" \ -# ] -# adi_ip_properties_lite jesd204_rx -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl' ignored by IP packager. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_data_r' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_header_r' has a dependency on the module local parameter or undefined parameter 'HW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_charisk_r' has a dependency on the module local parameter or undefined parameter 'CW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_notintable_r' has a dependency on the module local parameter or undefined parameter 'CW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_disperr_r' has a dependency on the module local parameter or undefined parameter 'CW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'rx_data_s' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'phy' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'phy_block' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'phy_char_align' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'event_unexpected_lane_error' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_ctrl' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_lane_cgs' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_lane_emb' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((8 * NUM_LANES) - 1):0' is present in all ports of the interface 'status_err_cnt'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port lane_frame_align on bus interface abstraction jesd204_rx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port lane_latency_ready on bus interface abstraction jesd204_rx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status' of definition 'analog.com:interface:jesd204_rx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'event' of definition 'analog.com:interface:jesd204_tx_event:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_err_statistics_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'lmfc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-818] Not transferring value dependency attribute "((spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) ? 8 : 4)" into user parameter "DATA_PATH_WIDTH". -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ilas_config_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'phy': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'phy_block': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'phy_block': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'phy_en_char_align' and definition port 'EN'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'phy_char_align': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_ctrl_state' and definition port 'ctrl_state'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_cgs_state' and definition port 'lane_cgs_state'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_emb_state' and definition port 'lane_emb_state'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_ifs_ready' and definition port 'lane_ifs_ready'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_latency' and definition port 'lane_latency'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_err_statistics_cnt' and definition port 'err_statistics_cnt'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "lane_frame_align" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "lane_latency_ready" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'lmfc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'lmfc_clk': FREQ_HZ bus parameter is missing for output clock interface. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_ttcl jesd204_rx "jesd204_rx_constr.ttcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:jesd204_common:1.0 \ -# } -# set_property display_name "ADI JESD204 Receive" [ipx::current_core] -# set_property description "ADI JESD204 Receive" [ipx::current_core] -# adi_add_multi_bus 16 "rx_phy" "slave" \ -# "xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0" \ -# "xilinx.com:display_jesd204:jesd204_rx_bus:1.0" \ -# [list \ -# { "phy_data" "rxdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \ -# { "phy_charisk" "rxcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \ -# { "phy_disperr" "rxdisperr" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \ -# { "phy_notintable" "rxnotintable" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \ -# { "phy_header" "rxheader" 2} \ -# { "phy_block_sync" "rxblock_sync" 1} \ -# ] \ -# "(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})" -# adi_add_bus "rx_cfg" "slave" \ -# "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_cfg:1.0" \ -# { \ -# { "cfg_lanes_disable" "lanes_disable" } \ -# { "cfg_links_disable" "links_disable" } \ -# { "cfg_beats_per_multiframe" "beats_per_multiframe" } \ -# { "cfg_octets_per_frame" "octets_per_frame" } \ -# { "cfg_lmfc_offset" "lmfc_offset" } \ -# { "cfg_sysref_oneshot" "sysref_oneshot" } \ -# { "cfg_sysref_disable" "sysref_disable" } \ -# { "cfg_buffer_delay" "buffer_delay" } \ -# { "cfg_buffer_early_release" "buffer_early_release" } \ -# { "cfg_disable_char_replacement" "disable_char_replacement" } \ -# { "ctrl_err_statistics_reset" "err_statistics_reset" } \ -# { "ctrl_err_statistics_mask" "err_statistics_mask" } \ -# { "cfg_disable_scrambler" "disable_scrambler" } \ -# { "cfg_frame_align_err_threshold" "frame_align_err_threshold" } \ -# } -# adi_add_bus "rx_status" "master" \ -# "analog.com:interface:jesd204_rx_status_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_status:1.0" \ -# { \ -# { "status_ctrl_state" "ctrl_state" } \ -# { "status_lane_cgs_state" "lane_cgs_state" } \ -# { "status_lane_emb_state" "lane_emb_state" } \ -# { "status_err_statistics_cnt" "err_statistics_cnt" } \ -# { "status_lane_ifs_ready" "lane_ifs_ready" } \ -# { "status_lane_latency" "lane_latency" } \ -# { "status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \ -# } -# adi_add_bus "rx_ilas_config" "master" \ -# "analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_ilas_config:1.0" \ -# { \ -# { "ilas_config_valid" "valid" } \ -# { "ilas_config_addr" "addr" } \ -# { "ilas_config_data" "data" } \ -# } -# adi_add_bus "rx_event" "master" \ -# "analog.com:interface:jesd204_rx_event_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_event:1.0" \ -# { \ -# { "event_sysref_alignment_error" "sysref_alignment_error" } \ -# { "event_sysref_edge" "sysref_edge" } \ -# { "event_frame_alignment_error" "frame_alignment_error" } \ -# { "event_unexpected_lane_state_error" "unexpected_lane_state_error" } \ -# } -# adi_add_bus_clock "clk" "rx_cfg:rx_ilas_config:rx_event:rx_status:rx_data" "reset" -# adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# adi_set_ports_dependency "sync" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# adi_set_ports_dependency "phy_en_char_align" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# set cc [ipx::current_core] -# set_property -dict [list \ -# driver_value 0 \ -# ] [ipx::get_ports phy_header -of_objects $cc] -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $page0 -# set_property -dict [list \ -# "display_name" "Link Layer mode" \ -# "tooltip" "Link Layer mode" \ -# "widget" "comboBox" \ -# ] $p -# set_property -dict [list \ -# value_validation_type pairs \ -# value_validation_pairs {64B66B 2 8B10B 1} \ -# ] [ipx::get_user_parameters $p -of_objects $cc] -# set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc] -# set_property -dict [list \ -# enablement_value false \ -# value_tcl_expr {expr $LINK_MODE*4} \ -# ] $param -# set param [ipx::add_user_parameter SYSREF_IOB $cc] -# set_property -dict {value_resolve_type user value_format bool value true} $param -# set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0] -# set_property -dict [list \ -# display_name {Place SYSREF in IOB} \ -# widget {checkBox} \ -# show_label true \ -# ] $param -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:25:18 2021... diff --git a/adi_library/jesd204/jesd204_rx/vivado.jou b/adi_library/jesd204/jesd204_rx/vivado.jou deleted file mode 100644 index 1c2dc532..00000000 --- a/adi_library/jesd204/jesd204_rx/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:25:03 2021 -# Process ID: 145992 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx -# Command line: vivado -mode batch -source jesd204_rx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx/vivado.jou -#----------------------------------------------------------- -source jesd204_rx_ip.tcl diff --git a/adi_library/jesd204/jesd204_rx/vivado.log b/adi_library/jesd204/jesd204_rx/vivado.log deleted file mode 100644 index 52f46ca0..00000000 --- a/adi_library/jesd204/jesd204_rx/vivado.log +++ /dev/null @@ -1,875 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:25:03 2021 -# Process ID: 145992 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx -# Command line: vivado -mode batch -source jesd204_rx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx/vivado.jou -#----------------------------------------------------------- -source jesd204_rx_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create jesd204_rx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files jesd204_rx [list \ -# "jesd204_rx_lane.v" \ -# "jesd204_rx_lane_64b.v" \ -# "jesd204_rx_header.v" \ -# "jesd204_rx_cgs.v" \ -# "jesd204_rx_ctrl.v" \ -# "jesd204_rx_ctrl_64b.v" \ -# "elastic_buffer.v" \ -# "error_monitor.v" \ -# "jesd204_ilas_monitor.v" \ -# "align_mux.v" \ -# "jesd204_lane_latency_monitor.v" \ -# "jesd204_rx_frame_mark.v" \ -# "jesd204_rx_frame_align_monitor.v" \ -# "jesd204_rx_constr.ttcl" \ -# "jesd204_rx.v" \ -# ] -# adi_ip_properties_lite jesd204_rx -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl' ignored by IP packager. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_data_r' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_header_r' has a dependency on the module local parameter or undefined parameter 'HW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_charisk_r' has a dependency on the module local parameter or undefined parameter 'CW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_notintable_r' has a dependency on the module local parameter or undefined parameter 'CW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_disperr_r' has a dependency on the module local parameter or undefined parameter 'CW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'rx_data_s' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'phy' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'phy_block' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'phy_char_align' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'event_unexpected_lane_error' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_ctrl' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_lane_cgs' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_lane_emb' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((8 * NUM_LANES) - 1):0' is present in all ports of the interface 'status_err_cnt'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port lane_frame_align on bus interface abstraction jesd204_rx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port lane_latency_ready on bus interface abstraction jesd204_rx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status' of definition 'analog.com:interface:jesd204_rx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'event' of definition 'analog.com:interface:jesd204_tx_event:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_err_statistics_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'lmfc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-818] Not transferring value dependency attribute "((spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) ? 8 : 4)" into user parameter "DATA_PATH_WIDTH". -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ilas_config_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'phy': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'phy_block': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'phy_block': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'phy_en_char_align' and definition port 'EN'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'phy_char_align': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_ctrl_state' and definition port 'ctrl_state'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_cgs_state' and definition port 'lane_cgs_state'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_emb_state' and definition port 'lane_emb_state'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_ifs_ready' and definition port 'lane_ifs_ready'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_latency' and definition port 'lane_latency'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_err_statistics_cnt' and definition port 'err_statistics_cnt'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "lane_frame_align" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "lane_latency_ready" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'lmfc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'lmfc_clk': FREQ_HZ bus parameter is missing for output clock interface. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_ttcl jesd204_rx "jesd204_rx_constr.ttcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:jesd204_common:1.0 \ -# } -# set_property display_name "ADI JESD204 Receive" [ipx::current_core] -# set_property description "ADI JESD204 Receive" [ipx::current_core] -# adi_add_multi_bus 16 "rx_phy" "slave" \ -# "xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0" \ -# "xilinx.com:display_jesd204:jesd204_rx_bus:1.0" \ -# [list \ -# { "phy_data" "rxdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \ -# { "phy_charisk" "rxcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \ -# { "phy_disperr" "rxdisperr" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \ -# { "phy_notintable" "rxnotintable" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \ -# { "phy_header" "rxheader" 2} \ -# { "phy_block_sync" "rxblock_sync" 1} \ -# ] \ -# "(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})" -# adi_add_bus "rx_cfg" "slave" \ -# "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_cfg:1.0" \ -# { \ -# { "cfg_lanes_disable" "lanes_disable" } \ -# { "cfg_links_disable" "links_disable" } \ -# { "cfg_beats_per_multiframe" "beats_per_multiframe" } \ -# { "cfg_octets_per_frame" "octets_per_frame" } \ -# { "cfg_lmfc_offset" "lmfc_offset" } \ -# { "cfg_sysref_oneshot" "sysref_oneshot" } \ -# { "cfg_sysref_disable" "sysref_disable" } \ -# { "cfg_buffer_delay" "buffer_delay" } \ -# { "cfg_buffer_early_release" "buffer_early_release" } \ -# { "cfg_disable_char_replacement" "disable_char_replacement" } \ -# { "ctrl_err_statistics_reset" "err_statistics_reset" } \ -# { "ctrl_err_statistics_mask" "err_statistics_mask" } \ -# { "cfg_disable_scrambler" "disable_scrambler" } \ -# { "cfg_frame_align_err_threshold" "frame_align_err_threshold" } \ -# } -# adi_add_bus "rx_status" "master" \ -# "analog.com:interface:jesd204_rx_status_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_status:1.0" \ -# { \ -# { "status_ctrl_state" "ctrl_state" } \ -# { "status_lane_cgs_state" "lane_cgs_state" } \ -# { "status_lane_emb_state" "lane_emb_state" } \ -# { "status_err_statistics_cnt" "err_statistics_cnt" } \ -# { "status_lane_ifs_ready" "lane_ifs_ready" } \ -# { "status_lane_latency" "lane_latency" } \ -# { "status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \ -# } -# adi_add_bus "rx_ilas_config" "master" \ -# "analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_ilas_config:1.0" \ -# { \ -# { "ilas_config_valid" "valid" } \ -# { "ilas_config_addr" "addr" } \ -# { "ilas_config_data" "data" } \ -# } -# adi_add_bus "rx_event" "master" \ -# "analog.com:interface:jesd204_rx_event_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_event:1.0" \ -# { \ -# { "event_sysref_alignment_error" "sysref_alignment_error" } \ -# { "event_sysref_edge" "sysref_edge" } \ -# { "event_frame_alignment_error" "frame_alignment_error" } \ -# { "event_unexpected_lane_state_error" "unexpected_lane_state_error" } \ -# } -# adi_add_bus_clock "clk" "rx_cfg:rx_ilas_config:rx_event:rx_status:rx_data" "reset" -# adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# adi_set_ports_dependency "sync" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# adi_set_ports_dependency "phy_en_char_align" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# set cc [ipx::current_core] -# set_property -dict [list \ -# driver_value 0 \ -# ] [ipx::get_ports phy_header -of_objects $cc] -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $page0 -# set_property -dict [list \ -# "display_name" "Link Layer mode" \ -# "tooltip" "Link Layer mode" \ -# "widget" "comboBox" \ -# ] $p -# set_property -dict [list \ -# value_validation_type pairs \ -# value_validation_pairs {64B66B 2 8B10B 1} \ -# ] [ipx::get_user_parameters $p -of_objects $cc] -# set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc] -# set_property -dict [list \ -# enablement_value false \ -# value_tcl_expr {expr $LINK_MODE*4} \ -# ] $param -# set param [ipx::add_user_parameter SYSREF_IOB $cc] -# set_property -dict {value_resolve_type user value_format bool value true} $param -# set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0] -# set_property -dict [list \ -# display_name {Place SYSREF in IOB} \ -# widget {checkBox} \ -# show_label true \ -# ] $param -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:25:18 2021... diff --git a/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.log b/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.log deleted file mode 100644 index 231577de..00000000 --- a/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.log +++ /dev/null @@ -1,713 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source jesd204_rx_static_config_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create jesd204_rx_static_config -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files jesd204_rx_static_config [list \ -# "jesd204_rx_static_config.v" \ -# ] -# adi_ip_properties_lite jesd204_rx_static_config -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_lanes_disable' and definition port 'lanes_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_links_disable' and definition port 'links_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_beats_per_multiframe' and definition port 'beats_per_multiframe'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_octets_per_frame' and definition port 'octets_per_frame'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_lmfc_offset' and definition port 'lmfc_offset'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_buffer_early_release' and definition port 'buffer_early_release'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_buffer_delay' and definition port 'buffer_delay'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_disable_char_replacement' and definition port 'disable_char_replacement'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_disable_scrambler' and definition port 'disable_scrambler'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_frame_align_err_threshold' and definition port 'frame_align_err_threshold'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "rx_cfg" "master" \ -# "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_cfg:1.0" \ -# { \ -# { "cfg_lanes_disable" "lanes_disable" } \ -# { "cfg_beats_per_multiframe" "beats_per_multiframe" } \ -# { "cfg_octets_per_frame" "octets_per_frame" } \ -# { "cfg_lmfc_offset" "lmfc_offset" } \ -# { "cfg_sysref_oneshot" "sysref_oneshot" } \ -# { "cfg_sysref_disable" "sysref_disable" } \ -# { "cfg_buffer_early_release" "buffer_early_release" } \ -# { "cfg_frame_align_err_threshold" "frame_align_err_threshold" } \ -# } -# adi_add_bus_clock "clk" "rx_cfg" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:28 2021... diff --git a/adi_library/jesd204/jesd204_rx_static_config/vivado.jou b/adi_library/jesd204/jesd204_rx_static_config/vivado.jou deleted file mode 100644 index f04f56c2..00000000 --- a/adi_library/jesd204/jesd204_rx_static_config/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:17:21 2021 -# Process ID: 6777 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config -# Command line: vivado -mode batch -source jesd204_rx_static_config_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config/vivado.jou -#----------------------------------------------------------- -source jesd204_rx_static_config_ip.tcl diff --git a/adi_library/jesd204/jesd204_rx_static_config/vivado.log b/adi_library/jesd204/jesd204_rx_static_config/vivado.log deleted file mode 100644 index 360295e7..00000000 --- a/adi_library/jesd204/jesd204_rx_static_config/vivado.log +++ /dev/null @@ -1,718 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:17:21 2021 -# Process ID: 6777 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config -# Command line: vivado -mode batch -source jesd204_rx_static_config_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config/vivado.jou -#----------------------------------------------------------- -source jesd204_rx_static_config_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create jesd204_rx_static_config -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files jesd204_rx_static_config [list \ -# "jesd204_rx_static_config.v" \ -# ] -# adi_ip_properties_lite jesd204_rx_static_config -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_lanes_disable' and definition port 'lanes_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_links_disable' and definition port 'links_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_beats_per_multiframe' and definition port 'beats_per_multiframe'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_octets_per_frame' and definition port 'octets_per_frame'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_lmfc_offset' and definition port 'lmfc_offset'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_buffer_early_release' and definition port 'buffer_early_release'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_buffer_delay' and definition port 'buffer_delay'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_disable_char_replacement' and definition port 'disable_char_replacement'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_disable_scrambler' and definition port 'disable_scrambler'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_frame_align_err_threshold' and definition port 'frame_align_err_threshold'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "rx_cfg" "master" \ -# "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \ -# "analog.com:interface:jesd204_rx_cfg:1.0" \ -# { \ -# { "cfg_lanes_disable" "lanes_disable" } \ -# { "cfg_beats_per_multiframe" "beats_per_multiframe" } \ -# { "cfg_octets_per_frame" "octets_per_frame" } \ -# { "cfg_lmfc_offset" "lmfc_offset" } \ -# { "cfg_sysref_oneshot" "sysref_oneshot" } \ -# { "cfg_sysref_disable" "sysref_disable" } \ -# { "cfg_buffer_early_release" "buffer_early_release" } \ -# { "cfg_frame_align_err_threshold" "frame_align_err_threshold" } \ -# } -# adi_add_bus_clock "clk" "rx_cfg" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:28 2021... diff --git a/adi_library/jesd204/jesd204_tx/jesd204_tx_ip.log b/adi_library/jesd204/jesd204_tx/jesd204_tx_ip.log deleted file mode 100644 index a0aa785a..00000000 --- a/adi_library/jesd204/jesd204_tx/jesd204_tx_ip.log +++ /dev/null @@ -1,852 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source jesd204_tx_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create jesd204_tx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files jesd204_tx [list \ -# "jesd204_tx_lane.v" \ -# "jesd204_tx_lane_64b.v" \ -# "jesd204_tx_header.v" \ -# "jesd204_tx_ctrl.v" \ -# "jesd204_tx_constr.ttcl" \ -# "jesd204_tx.v" -# ] -# adi_ip_properties_lite jesd204_tx -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl' ignored by IP packager. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_data_r' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_charisk_r' has a dependency on the module local parameter or undefined parameter 'CW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_header_r' has a dependency on the module local parameter or undefined parameter 'HW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'ilas_data' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-5150] The Range '(NUM_LINKS - 1):0' is present in all ports of the interface 'status'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_manual_request' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'phy' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'interface_if_gt_tx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port buffer_early_release on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port buffer_delay on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port frame_align_err_threshold on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'event' of definition 'analog.com:interface:jesd204_tx_event:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl' of definition 'analog.com:interface:jesd204_tx_ctrl:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'lmfc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-818] Not transferring value dependency attribute "(LINK_MODE1 ? 8 : 4)" into user parameter "DATA_PATH_WIDTH". -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_manual_request': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_manual_request': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'phy_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'phy': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "buffer_early_release" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "buffer_delay" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "frame_align_err_threshold" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'lmfc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'lmfc_clk': FREQ_HZ bus parameter is missing for output clock interface. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_ttcl jesd204_tx "jesd204_tx_constr.ttcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:jesd204_common:1.0 \ -# analog.com:user:util_cdc:1.0 \ -# } -# set_property display_name "ADI JESD204 Transmit" [ipx::current_core] -# set_property description "ADI JESD204 Transmit" [ipx::current_core] -# adi_add_bus "tx_data" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { \ -# { "tx_valid" "TVALID" } \ -# { "tx_ready" "TREADY" } \ -# { "tx_data" "TDATA" } \ -# } -# adi_add_multi_bus 16 "tx_phy" "master" \ -# "xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0" \ -# "xilinx.com:display_jesd204:jesd204_tx_bus:1.0" \ -# [list \ -# { "phy_data" "txdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \ -# { "phy_charisk" "txcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \ -# { "phy_header" "txheader" 2} \ -# ] \ -# "(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})" -# adi_add_bus "tx_cfg" "slave" \ -# "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_cfg:1.0" \ -# { \ -# { "cfg_lanes_disable" "lanes_disable" } \ -# { "cfg_links_disable" "links_disable" } \ -# { "cfg_beats_per_multiframe" "beats_per_multiframe" } \ -# { "cfg_octets_per_frame" "octets_per_frame" } \ -# { "cfg_lmfc_offset" "lmfc_offset" } \ -# { "cfg_sysref_oneshot" "sysref_oneshot" } \ -# { "cfg_sysref_disable" "sysref_disable" } \ -# { "cfg_continuous_cgs" "continuous_cgs" } \ -# { "cfg_continuous_ilas" "continuous_ilas" } \ -# { "cfg_skip_ilas" "skip_ilas" } \ -# { "cfg_mframes_per_ilas" "mframes_per_ilas" } \ -# { "cfg_disable_char_replacement" "disable_char_replacement" } \ -# { "cfg_disable_scrambler" "disable_scrambler" } \ -# } -# adi_add_bus "tx_ilas_config" "master" \ -# "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_ilas_config:1.0" \ -# { \ -# { "ilas_config_rd" "rd" } \ -# { "ilas_config_addr" "addr" } \ -# { "ilas_config_data" "data" } \ -# } -# adi_add_bus "tx_event" "master" \ -# "analog.com:interface:jesd204_tx_event_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_event:1.0" \ -# { \ -# { "event_sysref_alignment_error" "sysref_alignment_error" } \ -# { "event_sysref_edge" "sysref_edge" } \ -# } -# adi_add_bus "tx_status" "master" \ -# "analog.com:interface:jesd204_tx_status_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_status:1.0" \ -# { \ -# { "status_state" "state" } \ -# { "status_sync" "sync" } \ -# } -# adi_add_bus "tx_ctrl" "slave" \ -# "analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_ctrl:1.0" \ -# { \ -# { "ctrl_manual_sync_request" "manual_sync_request" } \ -# } -# adi_add_bus_clock "clk" "tx_data:tx_cfg:tx_ilas_config:tx_event:tx_status:tx_ctrl" \ -# "reset" -# adi_set_bus_dependency "tx_ilas_config" "tx_ilas_config" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# adi_set_bus_dependency "tx_ctrl" "tx_ctrl" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# adi_set_ports_dependency "sync" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# set cc [ipx::current_core] -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $page0 -# set_property -dict [list \ -# "display_name" "Link Layer mode" \ -# "tooltip" "Link Layer mode" \ -# "widget" "comboBox" \ -# ] $p -# set_property -dict [list \ -# value_validation_type pairs \ -# value_validation_pairs {64B66B 2 8B10B 1} \ -# ] [ipx::get_user_parameters $p -of_objects $cc] -# set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc] -# set_property -dict [list \ -# enablement_value false \ -# value_tcl_expr {expr $LINK_MODE*4} \ -# ] $param -# set param [ipx::add_user_parameter SYSREF_IOB $cc] -# set_property -dict {value_resolve_type user value_format bool value true} $param -# set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0] -# set_property -dict [list \ -# display_name {Place SYSREF in IOB} \ -# widget {checkBox} \ -# show_label true \ -# ] $param -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:38 2021... diff --git a/adi_library/jesd204/jesd204_tx/vivado.jou b/adi_library/jesd204/jesd204_tx/vivado.jou deleted file mode 100644 index 3abd37ab..00000000 --- a/adi_library/jesd204/jesd204_tx/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:17:28 2021 -# Process ID: 6846 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx -# Command line: vivado -mode batch -source jesd204_tx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx/vivado.jou -#----------------------------------------------------------- -source jesd204_tx_ip.tcl diff --git a/adi_library/jesd204/jesd204_tx/vivado.log b/adi_library/jesd204/jesd204_tx/vivado.log deleted file mode 100644 index 49a96eaf..00000000 --- a/adi_library/jesd204/jesd204_tx/vivado.log +++ /dev/null @@ -1,857 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:17:28 2021 -# Process ID: 6846 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx -# Command line: vivado -mode batch -source jesd204_tx_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx/vivado.jou -#----------------------------------------------------------- -source jesd204_tx_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create jesd204_tx -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files jesd204_tx [list \ -# "jesd204_tx_lane.v" \ -# "jesd204_tx_lane_64b.v" \ -# "jesd204_tx_header.v" \ -# "jesd204_tx_ctrl.v" \ -# "jesd204_tx_constr.ttcl" \ -# "jesd204_tx.v" -# ] -# adi_ip_properties_lite jesd204_tx -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl' ignored by IP packager. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_data_r' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_charisk_r' has a dependency on the module local parameter or undefined parameter 'CW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_header_r' has a dependency on the module local parameter or undefined parameter 'HW'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'ilas_data' has a dependency on the module local parameter or undefined parameter 'DW'. -WARNING: [IP_Flow 19-5150] The Range '(NUM_LINKS - 1):0' is present in all ports of the interface 'status'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_manual_request' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'phy' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'tx' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'interface_if_gt_tx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port buffer_early_release on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port buffer_delay on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port frame_align_err_threshold on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'event' of definition 'analog.com:interface:jesd204_tx_event:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl' of definition 'analog.com:interface:jesd204_tx_ctrl:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'lmfc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-818] Not transferring value dependency attribute "(LINK_MODE1 ? 8 : 4)" into user parameter "DATA_PATH_WIDTH". -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_manual_request': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_manual_request': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'phy_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'phy': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "buffer_early_release" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "buffer_delay" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "frame_align_err_threshold" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'lmfc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'lmfc_clk': FREQ_HZ bus parameter is missing for output clock interface. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_ttcl jesd204_tx "jesd204_tx_constr.ttcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:jesd204_common:1.0 \ -# analog.com:user:util_cdc:1.0 \ -# } -# set_property display_name "ADI JESD204 Transmit" [ipx::current_core] -# set_property description "ADI JESD204 Transmit" [ipx::current_core] -# adi_add_bus "tx_data" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { \ -# { "tx_valid" "TVALID" } \ -# { "tx_ready" "TREADY" } \ -# { "tx_data" "TDATA" } \ -# } -# adi_add_multi_bus 16 "tx_phy" "master" \ -# "xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0" \ -# "xilinx.com:display_jesd204:jesd204_tx_bus:1.0" \ -# [list \ -# { "phy_data" "txdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \ -# { "phy_charisk" "txcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \ -# { "phy_header" "txheader" 2} \ -# ] \ -# "(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})" -# adi_add_bus "tx_cfg" "slave" \ -# "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_cfg:1.0" \ -# { \ -# { "cfg_lanes_disable" "lanes_disable" } \ -# { "cfg_links_disable" "links_disable" } \ -# { "cfg_beats_per_multiframe" "beats_per_multiframe" } \ -# { "cfg_octets_per_frame" "octets_per_frame" } \ -# { "cfg_lmfc_offset" "lmfc_offset" } \ -# { "cfg_sysref_oneshot" "sysref_oneshot" } \ -# { "cfg_sysref_disable" "sysref_disable" } \ -# { "cfg_continuous_cgs" "continuous_cgs" } \ -# { "cfg_continuous_ilas" "continuous_ilas" } \ -# { "cfg_skip_ilas" "skip_ilas" } \ -# { "cfg_mframes_per_ilas" "mframes_per_ilas" } \ -# { "cfg_disable_char_replacement" "disable_char_replacement" } \ -# { "cfg_disable_scrambler" "disable_scrambler" } \ -# } -# adi_add_bus "tx_ilas_config" "master" \ -# "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_ilas_config:1.0" \ -# { \ -# { "ilas_config_rd" "rd" } \ -# { "ilas_config_addr" "addr" } \ -# { "ilas_config_data" "data" } \ -# } -# adi_add_bus "tx_event" "master" \ -# "analog.com:interface:jesd204_tx_event_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_event:1.0" \ -# { \ -# { "event_sysref_alignment_error" "sysref_alignment_error" } \ -# { "event_sysref_edge" "sysref_edge" } \ -# } -# adi_add_bus "tx_status" "master" \ -# "analog.com:interface:jesd204_tx_status_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_status:1.0" \ -# { \ -# { "status_state" "state" } \ -# { "status_sync" "sync" } \ -# } -# adi_add_bus "tx_ctrl" "slave" \ -# "analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_ctrl:1.0" \ -# { \ -# { "ctrl_manual_sync_request" "manual_sync_request" } \ -# } -# adi_add_bus_clock "clk" "tx_data:tx_cfg:tx_ilas_config:tx_event:tx_status:tx_ctrl" \ -# "reset" -# adi_set_bus_dependency "tx_ilas_config" "tx_ilas_config" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# adi_set_bus_dependency "tx_ctrl" "tx_ctrl" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# adi_set_ports_dependency "sync" \ -# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" -# set cc [ipx::current_core] -# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -# set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] -# ipgui::move_param -component $cc -order 0 $p -parent $page0 -# set_property -dict [list \ -# "display_name" "Link Layer mode" \ -# "tooltip" "Link Layer mode" \ -# "widget" "comboBox" \ -# ] $p -# set_property -dict [list \ -# value_validation_type pairs \ -# value_validation_pairs {64B66B 2 8B10B 1} \ -# ] [ipx::get_user_parameters $p -of_objects $cc] -# set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc] -# set_property -dict [list \ -# enablement_value false \ -# value_tcl_expr {expr $LINK_MODE*4} \ -# ] $param -# set param [ipx::add_user_parameter SYSREF_IOB $cc] -# set_property -dict {value_resolve_type user value_format bool value true} $param -# set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0] -# set_property -dict [list \ -# display_name {Place SYSREF in IOB} \ -# widget {checkBox} \ -# show_label true \ -# ] $param -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:38 2021... diff --git a/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.log b/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.log deleted file mode 100644 index ad6ed2d6..00000000 --- a/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.log +++ /dev/null @@ -1,739 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source jesd204_tx_static_config_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create jesd204_tx_static_config -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx_static_config'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files jesd204_tx_static_config [list \ -# "jesd204_tx_static_config.v" \ -# "jesd204_ilas_cfg_static.v" \ -# ] -# adi_ip_properties_lite jesd204_tx_static_config -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port buffer_early_release on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port buffer_delay on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port frame_align_err_threshold on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ilas_config_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_lanes_disable' and definition port 'lanes_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_links_disable' and definition port 'links_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_beats_per_multiframe' and definition port 'beats_per_multiframe'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_octets_per_frame' and definition port 'octets_per_frame'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_lmfc_offset' and definition port 'lmfc_offset'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_disable_char_replacement' and definition port 'disable_char_replacement'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_disable_scrambler' and definition port 'disable_scrambler'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "buffer_early_release" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "buffer_delay" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "frame_align_err_threshold" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "tx_cfg" "master" \ -# "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_cfg:1.0" \ -# { \ -# { "cfg_lanes_disable" "lanes_disable" } \ -# { "cfg_beats_per_multiframe" "beats_per_multiframe" } \ -# { "cfg_octets_per_frame" "octets_per_frame" } \ -# { "cfg_lmfc_offset" "lmfc_offset" } \ -# { "cfg_sysref_oneshot" "sysref_oneshot" } \ -# { "cfg_sysref_disable" "sysref_disable" } \ -# { "cfg_continuous_cgs" "continuous_cgs" } \ -# { "cfg_continuous_ilas" "continuous_ilas" } \ -# { "cfg_skip_ilas" "skip_ilas" } \ -# { "cfg_mframes_per_ilas" "mframes_per_ilas" } \ -# { "cfg_disable_char_replacement" "disable_char_replacement" } \ -# { "cfg_disable_scrambler" "disable_scrambler" } \ -# } -# adi_add_bus "tx_ilas_config" "slave" \ -# "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_ilas_config:1.0" \ -# { \ -# { "ilas_config_rd" "rd" } \ -# { "ilas_config_addr" "addr" } \ -# { "ilas_config_data" "data" } \ -# } -# adi_add_bus_clock "core_clk" "tx_cfg:tx_ilas_config" -WARNING: [IP_Flow 19-529] Port Map 'CLK': Port named 'core_clk' does not exist. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:46 2021... diff --git a/adi_library/jesd204/jesd204_tx_static_config/vivado.jou b/adi_library/jesd204/jesd204_tx_static_config/vivado.jou deleted file mode 100644 index a2b352dc..00000000 --- a/adi_library/jesd204/jesd204_tx_static_config/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:17:39 2021 -# Process ID: 6912 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx_static_config -# Command line: vivado -mode batch -source jesd204_tx_static_config_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx_static_config/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx_static_config/vivado.jou -#----------------------------------------------------------- -source jesd204_tx_static_config_ip.tcl diff --git a/adi_library/jesd204/jesd204_tx_static_config/vivado.log b/adi_library/jesd204/jesd204_tx_static_config/vivado.log deleted file mode 100644 index 5836adf4..00000000 --- a/adi_library/jesd204/jesd204_tx_static_config/vivado.log +++ /dev/null @@ -1,744 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:17:39 2021 -# Process ID: 6912 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx_static_config -# Command line: vivado -mode batch -source jesd204_tx_static_config_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx_static_config/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx_static_config/vivado.jou -#----------------------------------------------------------- -source jesd204_tx_static_config_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create jesd204_tx_static_config -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx_static_config'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files jesd204_tx_static_config [list \ -# "jesd204_tx_static_config.v" \ -# "jesd204_ilas_cfg_static.v" \ -# ] -# adi_ip_properties_lite jesd204_tx_static_config -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port buffer_early_release on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port buffer_delay on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port frame_align_err_threshold on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ilas_config_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_lanes_disable' and definition port 'lanes_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_links_disable' and definition port 'links_disable'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_beats_per_multiframe' and definition port 'beats_per_multiframe'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_octets_per_frame' and definition port 'octets_per_frame'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_lmfc_offset' and definition port 'lmfc_offset'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_disable_char_replacement' and definition port 'disable_char_replacement'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_disable_scrambler' and definition port 'disable_scrambler'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "buffer_early_release" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "buffer_delay" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "frame_align_err_threshold" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "tx_cfg" "master" \ -# "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_cfg:1.0" \ -# { \ -# { "cfg_lanes_disable" "lanes_disable" } \ -# { "cfg_beats_per_multiframe" "beats_per_multiframe" } \ -# { "cfg_octets_per_frame" "octets_per_frame" } \ -# { "cfg_lmfc_offset" "lmfc_offset" } \ -# { "cfg_sysref_oneshot" "sysref_oneshot" } \ -# { "cfg_sysref_disable" "sysref_disable" } \ -# { "cfg_continuous_cgs" "continuous_cgs" } \ -# { "cfg_continuous_ilas" "continuous_ilas" } \ -# { "cfg_skip_ilas" "skip_ilas" } \ -# { "cfg_mframes_per_ilas" "mframes_per_ilas" } \ -# { "cfg_disable_char_replacement" "disable_char_replacement" } \ -# { "cfg_disable_scrambler" "disable_scrambler" } \ -# } -# adi_add_bus "tx_ilas_config" "slave" \ -# "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \ -# "analog.com:interface:jesd204_tx_ilas_config:1.0" \ -# { \ -# { "ilas_config_rd" "rd" } \ -# { "ilas_config_addr" "addr" } \ -# { "ilas_config_data" "data" } \ -# } -# adi_add_bus_clock "core_clk" "tx_cfg:tx_ilas_config" -WARNING: [IP_Flow 19-529] Port Map 'CLK': Port named 'core_clk' does not exist. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:46 2021... diff --git a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_ip.log b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_ip.log deleted file mode 100644 index 05c9fb30..00000000 --- a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_ip.log +++ /dev/null @@ -1,1672 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_spi_engine_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_spi_engine -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_spi_engine [list \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "axi_spi_engine_constr.ttcl" \ -# "axi_spi_engine.v" \ -# ] -# adi_ip_properties axi_spi_engine -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'offload_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'offload_sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload0_cmd_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload0_sdo_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'offload0_cmd_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'offload0_sdo_data'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'up'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'offload0_cmd_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'offload0_sdo_data'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'up'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'offload_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'offload0_cmd_wr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'offload0_sdo_wr'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'offload_sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'offload0_cmd_wr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'offload0_sdo_wr'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port CMD_WR_EN on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port CMD_WR_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ENABLE on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port MEM_RESET on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ENABLED on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'offload0_wr_data'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'up'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'spi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'up_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 'spi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'spi_resetn'. -INFO: [IP_Flow 19-4728] Bus Interface 'up_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rstn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_4': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_5': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_6': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_7': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'offload_sync_ready' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_ready': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_valid': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_ready' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data_valid' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'offload_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'offload_sync_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_12': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_13': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_14': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_15': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'offload_sync_ready' and definition port 'SYNC_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'offload_sync_valid' and definition port 'SYNC_VALID'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'offload_sync_data' and definition port 'SYNC_DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "ENABLE" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3157] Bus Interface 'up_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'up_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'spi_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'up_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_ttcl axi_spi_engine "axi_spi_engine_constr.ttcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_axis_fifo:1.0 \ -# analog.com:user:util_cdc:1.0 \ -# } -# adi_add_bus "spi_engine_ctrl" "master" \ -# "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_ctrl:1.0" \ -# { -# {"cmd_ready" "CMD_READY"} \ -# {"cmd_valid" "CMD_VALID"} \ -# {"cmd_data" "CMD_DATA"} \ -# {"sdo_data_ready" "SDO_READY"} \ -# {"sdo_data_valid" "SDO_VALID"} \ -# {"sdo_data" "SDO_DATA"} \ -# {"sdi_data_ready" "SDI_READY"} \ -# {"sdi_data_valid" "SDI_VALID"} \ -# {"sdi_data" "SDI_DATA"} \ -# {"sync_ready" "SYNC_READY"} \ -# {"sync_valid" "SYNC_VALID"} \ -# {"sync_data" "SYNC_DATA"} \ -# } -# adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" "master" -# adi_add_bus "spi_engine_offload_ctrl0" "master" \ -# "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_offload_ctrl:1.0" \ -# { \ -# { "offload0_cmd_wr_en" "CMD_WR_EN"} \ -# { "offload0_cmd_wr_data" "CMD_WR_DATA"} \ -# { "offload0_sdo_wr_en" "SDO_WR_EN"} \ -# { "offload0_sdo_wr_data" "SDO_WR_DATA"} \ -# { "offload0_enable" "ENABLE"} \ -# { "offload0_enabled" "ENABLED"} \ -# { "offload0_mem_reset" "MEM_RESET"} \ -# { "offload_sync_ready" "SYNC_READY"} \ -# { "offload_sync_valid" "SYNC_VALID"} \ -# { "offload_sync_data" "SYNC_DATA"} \ -# } -# adi_add_bus_clock "s_axi_aclk" "spi_engine_offload_ctrl0:s_axi" "s_axi_aresetn" -# foreach port {"up_clk" "up_rstn" "up_wreq" "up_waddr" "up_wdata" "up_rreq" "up_raddr"} { -# set_property DRIVER_VALUE "0" [ipx::get_ports $port] -# } -# adi_set_bus_dependency "spi_engine_offload_ctrl0" "spi_engine_offload_ctrl0" \ -# "(spirit:decode(id('MODELPARAM_VALUE.NUM_OFFLOAD')) > 0)" -# adi_set_bus_dependency "s_axi" "s_axi" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 0)" -# adi_set_ports_dependency "up_clk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_rstn" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_wreq" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_waddr" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_wdata" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_rreq" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_raddr" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_wack" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_rdata" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_rack" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# set cc [ipx::current_core] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "255" \ -# ] \ -# [ipx::get_user_parameters ID -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters CMD_FIFO_ADDRESS_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters SYNC_FIFO_ADDRESS_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters SDO_FIFO_ADDRESS_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters SDI_FIFO_ADDRESS_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "pairs" \ -# "value_validation_pairs" { \ -# "AXI4 Memory Mapped" "0" \ -# "ADI uP FIFO" "1" \ -# } \ -# ] \ -# [ipx::get_user_parameters MM_IF_TYPE -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_user_parameters ASYNC_SPI_CLK -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_hdl_parameters ASYNC_SPI_CLK -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "8" \ -# ] \ -# [ipx::get_user_parameters NUM_OFFLOAD -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters OFFLOAD0_CMD_MEM_ADDRESS_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters OFFLOAD0_SDO_MEM_ADDRESS_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "8" \ -# "value_validation_range_maximum" "256" \ -# ] \ -# [ipx::get_user_parameters DATA_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "8" \ -# ] \ -# [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] -# ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] -# ipx::save_core [ipx::current_core] -# ipgui::add_page -name {AXI SPI Engine soft-controller} -component [ipx::current_core] -display_name {AXI SPI Engine soft-controller} -# set page0 [ipgui::get_pagespec -name "AXI SPI Engine soft-controller" -component $cc] -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration" ] -# ipgui::add_param -name "ID" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Core ID" \ -# "tooltip" "\[ID\] Core instance ID" \ -# ] [ipgui::get_guiparamspec -name "ID" -component $cc] -# ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Parallel data width" \ -# "tooltip" "\[DATA_WIDTH\] Define the data interface width" -# ] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] -# ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Number of MISO lines" \ -# "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ -# ] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] -# ipgui::add_param -name "MM_IF_TYPE" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Memory Mapped Interface Type" \ -# "tooltip" "\[MM_IF_TYPE\] Define the memory mapped interface type" \ -# ] [ipgui::get_guiparamspec -name "MM_IF_TYPE" -component $cc] -# ipgui::add_param -name "ASYNC_SPI_CLK" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Asynchronous core clock" \ -# "tooltip" "\[ASYNC_SPI_CLK\] Define the relationship between the core clock and the memory mapped interface clock" \ -# ] [ipgui::get_guiparamspec -name "ASYNC_SPI_CLK" -component $cc] -# set cmd_stream_fifo_group [ipgui::add_group -name "Command stream FIFO configuration" -component $cc \ -# -parent $page0 -display_name "Command stream FIFO configuration" ] -# ipgui::add_param -name "CMD_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group -# set_property -dict [list \ -# "display_name" "Command FIFO address width" \ -# "tooltip" "\[CMD_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "CMD_FIFO_ADDRESS_WIDTH" -component $cc] -# ipgui::add_param -name "SYNC_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group -# set_property -dict [list \ -# "display_name" "SYNC FIFO address width" \ -# "tooltip" "\[SYNC_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "SYNC_FIFO_ADDRESS_WIDTH" -component $cc] -# ipgui::add_param -name "SDO_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group -# set_property -dict [list \ -# "display_name" "MOSI FIFO address width" \ -# "tooltip" "\[SDO_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "SDO_FIFO_ADDRESS_WIDTH" -component $cc] -# ipgui::add_param -name "SDI_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group -# set_property -dict [list \ -# "display_name" "MISO FIFO address width" \ -# "tooltip" "\[SDI_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "SDI_FIFO_ADDRESS_WIDTH" -component $cc] -# set offload_group [ipgui::add_group -name "Offload module configuration" -component $cc \ -# -parent $page0 -display_name "Offload module configuration" ] -# ipgui::add_param -name "NUM_OFFLOAD" -component $cc -parent $offload_group -# set_property -dict [list \ -# "display_name" "Number of offloads" \ -# "tooltip" "\[NUM_OFFLOAD\] Number of offloads" \ -# ] [ipgui::get_guiparamspec -name "NUM_OFFLOAD" -component $cc] -# ipgui::add_param -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -component $cc -parent $offload_group -# set_property -dict [list \ -# "display_name" "Offload command FIFO address width" \ -# "tooltip" "\[OFFLOAD0_CMD_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -component $cc] -# set_property enablement_tcl_expr {$NUM_OFFLOAD > 0} [ipx::get_user_parameters OFFLOAD0_CMD_MEM_ADDRESS_WIDTH -of_objects $cc] -# ipgui::add_param -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -component $cc -parent $offload_group -# set_property -dict [list \ -# "display_name" "Offload MOSI FIFO address width" \ -# "tooltip" "\[OFFLOAD0_SDO_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -component $cc] -# set_property enablement_tcl_expr {$NUM_OFFLOAD > 0} [ipx::get_user_parameters OFFLOAD0_SDO_MEM_ADDRESS_WIDTH -of_objects $cc] -# ipx::create_xgui_files $cc -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:07:42 2021... diff --git a/adi_library/spi_engine/axi_spi_engine/vivado.jou b/adi_library/spi_engine/axi_spi_engine/vivado.jou deleted file mode 100644 index 8d97d726..00000000 --- a/adi_library/spi_engine/axi_spi_engine/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:07:34 2021 -# Process ID: 3196 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine -# Command line: vivado -mode batch -source axi_spi_engine_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine/vivado.jou -#----------------------------------------------------------- -source axi_spi_engine_ip.tcl diff --git a/adi_library/spi_engine/axi_spi_engine/vivado.log b/adi_library/spi_engine/axi_spi_engine/vivado.log deleted file mode 100644 index 70015f29..00000000 --- a/adi_library/spi_engine/axi_spi_engine/vivado.log +++ /dev/null @@ -1,1677 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:07:34 2021 -# Process ID: 3196 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine -# Command line: vivado -mode batch -source axi_spi_engine_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine/vivado.jou -#----------------------------------------------------------- -source axi_spi_engine_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_spi_engine -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_spi_engine [list \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ -# "axi_spi_engine_constr.ttcl" \ -# "axi_spi_engine.v" \ -# ] -# adi_ip_properties axi_spi_engine -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/axi_spi_engine'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'offload_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'offload_sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload0_cmd_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload0_sdo_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_data_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sync_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'offload0_cmd_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'offload0_sdo_data'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'up'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'offload0_cmd_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'offload0_sdo_data'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'up'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'offload_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'offload0_cmd_wr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'offload0_sdo_wr'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'offload_sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'offload0_cmd_wr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'offload0_sdo_wr'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port CMD_WR_EN on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port CMD_WR_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ENABLE on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port MEM_RESET on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ENABLED on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'offload0_wr_data'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'up'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'spi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'up_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 'spi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'spi_resetn'. -INFO: [IP_Flow 19-4728] Bus Interface 'up_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rstn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_4': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_5': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_6': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_7': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_data_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'offload_sync_ready' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_ready': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_valid': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_ready' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data_valid' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'offload_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'offload_sync_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_12': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_13': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_14': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_15': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload0_cmd_wr_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'offload_sync_ready' and definition port 'SYNC_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'offload_sync_valid' and definition port 'SYNC_VALID'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'offload_sync_data' and definition port 'SYNC_DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "ENABLE" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3157] Bus Interface 'up_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'up_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'spi_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'up_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_ttcl axi_spi_engine "axi_spi_engine_constr.ttcl" -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_axis_fifo:1.0 \ -# analog.com:user:util_cdc:1.0 \ -# } -# adi_add_bus "spi_engine_ctrl" "master" \ -# "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_ctrl:1.0" \ -# { -# {"cmd_ready" "CMD_READY"} \ -# {"cmd_valid" "CMD_VALID"} \ -# {"cmd_data" "CMD_DATA"} \ -# {"sdo_data_ready" "SDO_READY"} \ -# {"sdo_data_valid" "SDO_VALID"} \ -# {"sdo_data" "SDO_DATA"} \ -# {"sdi_data_ready" "SDI_READY"} \ -# {"sdi_data_valid" "SDI_VALID"} \ -# {"sdi_data" "SDI_DATA"} \ -# {"sync_ready" "SYNC_READY"} \ -# {"sync_valid" "SYNC_VALID"} \ -# {"sync_data" "SYNC_DATA"} \ -# } -# adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" "master" -# adi_add_bus "spi_engine_offload_ctrl0" "master" \ -# "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_offload_ctrl:1.0" \ -# { \ -# { "offload0_cmd_wr_en" "CMD_WR_EN"} \ -# { "offload0_cmd_wr_data" "CMD_WR_DATA"} \ -# { "offload0_sdo_wr_en" "SDO_WR_EN"} \ -# { "offload0_sdo_wr_data" "SDO_WR_DATA"} \ -# { "offload0_enable" "ENABLE"} \ -# { "offload0_enabled" "ENABLED"} \ -# { "offload0_mem_reset" "MEM_RESET"} \ -# { "offload_sync_ready" "SYNC_READY"} \ -# { "offload_sync_valid" "SYNC_VALID"} \ -# { "offload_sync_data" "SYNC_DATA"} \ -# } -# adi_add_bus_clock "s_axi_aclk" "spi_engine_offload_ctrl0:s_axi" "s_axi_aresetn" -# foreach port {"up_clk" "up_rstn" "up_wreq" "up_waddr" "up_wdata" "up_rreq" "up_raddr"} { -# set_property DRIVER_VALUE "0" [ipx::get_ports $port] -# } -# adi_set_bus_dependency "spi_engine_offload_ctrl0" "spi_engine_offload_ctrl0" \ -# "(spirit:decode(id('MODELPARAM_VALUE.NUM_OFFLOAD')) > 0)" -# adi_set_bus_dependency "s_axi" "s_axi" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 0)" -# adi_set_ports_dependency "up_clk" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_rstn" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_wreq" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_waddr" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_wdata" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_rreq" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_raddr" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_wack" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_rdata" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# adi_set_ports_dependency "up_rack" \ -# "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" -# set cc [ipx::current_core] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "255" \ -# ] \ -# [ipx::get_user_parameters ID -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters CMD_FIFO_ADDRESS_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters SYNC_FIFO_ADDRESS_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters SDO_FIFO_ADDRESS_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters SDI_FIFO_ADDRESS_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "pairs" \ -# "value_validation_pairs" { \ -# "AXI4 Memory Mapped" "0" \ -# "ADI uP FIFO" "1" \ -# } \ -# ] \ -# [ipx::get_user_parameters MM_IF_TYPE -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_user_parameters ASYNC_SPI_CLK -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_hdl_parameters ASYNC_SPI_CLK -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "8" \ -# ] \ -# [ipx::get_user_parameters NUM_OFFLOAD -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters OFFLOAD0_CMD_MEM_ADDRESS_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters OFFLOAD0_SDO_MEM_ADDRESS_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "8" \ -# "value_validation_range_maximum" "256" \ -# ] \ -# [ipx::get_user_parameters DATA_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "8" \ -# ] \ -# [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] -# ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] -# ipx::save_core [ipx::current_core] -# ipgui::add_page -name {AXI SPI Engine soft-controller} -component [ipx::current_core] -display_name {AXI SPI Engine soft-controller} -# set page0 [ipgui::get_pagespec -name "AXI SPI Engine soft-controller" -component $cc] -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration" ] -# ipgui::add_param -name "ID" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Core ID" \ -# "tooltip" "\[ID\] Core instance ID" \ -# ] [ipgui::get_guiparamspec -name "ID" -component $cc] -# ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Parallel data width" \ -# "tooltip" "\[DATA_WIDTH\] Define the data interface width" -# ] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] -# ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Number of MISO lines" \ -# "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ -# ] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] -# ipgui::add_param -name "MM_IF_TYPE" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Memory Mapped Interface Type" \ -# "tooltip" "\[MM_IF_TYPE\] Define the memory mapped interface type" \ -# ] [ipgui::get_guiparamspec -name "MM_IF_TYPE" -component $cc] -# ipgui::add_param -name "ASYNC_SPI_CLK" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Asynchronous core clock" \ -# "tooltip" "\[ASYNC_SPI_CLK\] Define the relationship between the core clock and the memory mapped interface clock" \ -# ] [ipgui::get_guiparamspec -name "ASYNC_SPI_CLK" -component $cc] -# set cmd_stream_fifo_group [ipgui::add_group -name "Command stream FIFO configuration" -component $cc \ -# -parent $page0 -display_name "Command stream FIFO configuration" ] -# ipgui::add_param -name "CMD_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group -# set_property -dict [list \ -# "display_name" "Command FIFO address width" \ -# "tooltip" "\[CMD_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "CMD_FIFO_ADDRESS_WIDTH" -component $cc] -# ipgui::add_param -name "SYNC_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group -# set_property -dict [list \ -# "display_name" "SYNC FIFO address width" \ -# "tooltip" "\[SYNC_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "SYNC_FIFO_ADDRESS_WIDTH" -component $cc] -# ipgui::add_param -name "SDO_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group -# set_property -dict [list \ -# "display_name" "MOSI FIFO address width" \ -# "tooltip" "\[SDO_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "SDO_FIFO_ADDRESS_WIDTH" -component $cc] -# ipgui::add_param -name "SDI_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group -# set_property -dict [list \ -# "display_name" "MISO FIFO address width" \ -# "tooltip" "\[SDI_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "SDI_FIFO_ADDRESS_WIDTH" -component $cc] -# set offload_group [ipgui::add_group -name "Offload module configuration" -component $cc \ -# -parent $page0 -display_name "Offload module configuration" ] -# ipgui::add_param -name "NUM_OFFLOAD" -component $cc -parent $offload_group -# set_property -dict [list \ -# "display_name" "Number of offloads" \ -# "tooltip" "\[NUM_OFFLOAD\] Number of offloads" \ -# ] [ipgui::get_guiparamspec -name "NUM_OFFLOAD" -component $cc] -# ipgui::add_param -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -component $cc -parent $offload_group -# set_property -dict [list \ -# "display_name" "Offload command FIFO address width" \ -# "tooltip" "\[OFFLOAD0_CMD_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -component $cc] -# set_property enablement_tcl_expr {$NUM_OFFLOAD > 0} [ipx::get_user_parameters OFFLOAD0_CMD_MEM_ADDRESS_WIDTH -of_objects $cc] -# ipgui::add_param -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -component $cc -parent $offload_group -# set_property -dict [list \ -# "display_name" "Offload MOSI FIFO address width" \ -# "tooltip" "\[OFFLOAD0_SDO_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -component $cc] -# set_property enablement_tcl_expr {$NUM_OFFLOAD > 0} [ipx::get_user_parameters OFFLOAD0_SDO_MEM_ADDRESS_WIDTH -of_objects $cc] -# ipx::create_xgui_files $cc -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:07:42 2021... diff --git a/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_ip.log b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_ip.log deleted file mode 100644 index f480b415..00000000 --- a/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_ip.log +++ /dev/null @@ -1,968 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source spi_engine_execution_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create spi_engine_execution -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files spi_engine_execution [list \ -# "spi_engine_execution.v" \ -# ] -# adi_ip_properties_lite spi_engine_execution -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter2' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter2' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'bit_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'transfer_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'transfer_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_transfer_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_TRANSFER'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_write_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_WRITE'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_chipselect_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_CHIPSELECT'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_misc_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_MISC'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_sync_cmd' has a dependency on the module local parameter or undefined parameter 'MISC_SYNC'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_active_s' has a dependency on the module local parameter or undefined parameter 'CMD_CHIPSELECT'. -INFO: [IP_Flow 19-4821] For module 'spi_engine_execution', parameter 'SDO_DEFAULT' is inferred to be bitString format. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'interface_jesd204_tx_status'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_0' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_1' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_2' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_3' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_4' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_5' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_6' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_7' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_EN on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLE on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port MEM_RESET on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLED on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SYNC_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_spi_engine_offload_ctrl' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_spi_master' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_DATA on bus interface abstraction spi_engine_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SDO_READY on bus interface abstraction spi_engine_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SDO_VALID on bus interface abstraction spi_engine_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SDI_READY on bus interface abstraction spi_engine_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SDI_VALID on bus interface abstraction spi_engine_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SYNC_DATA on bus interface abstraction spi_engine_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_spi_engine_ctrl' of definition 'analog.com:interface:spi_engine_ctrl:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_valid' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data_ready' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_0': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_1': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_2': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_3': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_4': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_5': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_6': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_7': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "ENABLE" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "CMD_DATA" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDO_READY" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDO_VALID" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDI_READY" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDI_VALID" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# adi_add_bus "ctrl" "slave" \ -# "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_ctrl:1.0" \ -# { -# {"cmd_ready" "CMD_READY"} \ -# {"cmd_valid" "CMD_VALID"} \ -# {"cmd" "CMD_DATA"} \ -# {"sdo_data_ready" "SDO_READY"} \ -# {"sdo_data_valid" "SDO_VALID"} \ -# {"sdo_data" "SDO_DATA"} \ -# {"sdi_data_ready" "SDI_READY"} \ -# {"sdi_data_valid" "SDI_VALID"} \ -# {"sdi_data" "SDI_DATA"} \ -# {"sync_ready" "SYNC_READY"} \ -# {"sync_valid" "SYNC_VALID"} \ -# {"sync" "SYNC_DATA"} \ -# } -# adi_add_bus_clock "clk" "ctrl" "resetn" -# adi_add_bus "spi" "master" \ -# "analog.com:interface:spi_master_rtl:1.0" \ -# "analog.com:interface:spi_master:1.0" \ -# { -# {"sclk" "SCLK"} \ -# {"sdi" "SDI"} \ -# {"sdo" "SDO"} \ -# {"sdo_t" "SDO_T"} \ -# {"three_wire" "THREE_WIRE"} \ -# {"cs" "CS"} \ -# } -# adi_add_bus_clock "clk" "spi" "resetn" -# set cc [ipx::current_core] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "8" \ -# "value_validation_range_maximum" "256" \ -# ] \ -# [ipx::get_user_parameters DATA_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "32" \ -# ] \ -# [ipx::get_user_parameters NUM_OF_CS -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "8" \ -# ] \ -# [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_list" "0 1 2 3" \ -# ] \ -# [ipx::get_user_parameters DEFAULT_SPI_CFG -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "255" \ -# ] \ -# [ipx::get_user_parameters DEFAULT_CLK_DIV -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_list" "0 1" \ -# ] \ -# [ipx::get_user_parameters SDO_DEFAULT -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_user_parameters SDI_DELAY -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_hdl_parameters SDI_DELAY -of_objects $cc] -# ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] -# ipx::save_core [ipx::current_core] -# ipgui::add_page -name {SPI Engine execution} -component [ipx::current_core] -display_name {AXI SPI Engine execution} -# set page0 [ipgui::get_pagespec -name "SPI Engine execution" -component $cc] -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration" ] -# ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Parallel data width" \ -# "tooltip" "\[DATA_WIDTH\] Define the data interface width" -# ] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] -# ipgui::add_param -name "NUM_OF_CS" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Number of CSN lines" \ -# "tooltip" "\[NUM_OF_CS\] Define the number of chip select lines" \ -# ] [ipgui::get_guiparamspec -name "NUM_OF_CS" -component $cc] -# ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Number of MISO lines" \ -# "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ -# ] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] -# set spi_config_group [ipgui::add_group -name "SPI Configuration" -component $cc \ -# -parent $page0 -display_name "SPI Configuration" ] -# ipgui::add_param -name "DEFAULT_SPI_CFG" -component $cc -parent $spi_config_group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "Default SPI mode" \ -# "tooltip" "\[DEFAULT_SPI_CFG\] Define the default SPI configuration, bit 1 defines CPOL, bit 0 defines CPHA" -# ] [ipgui::get_guiparamspec -name "DEFAULT_SPI_CFG" -component $cc] -# ipgui::add_param -name "DEFAULT_CLK_DIV" -component $cc -parent $spi_config_group -# set_property -dict [list \ -# "display_name" "Default SCLK divider" \ -# "tooltip" "\[DEFAULT_CLK_DIV\] Define the default SCLK divider, fSCLK = fCoreClk / DEFAULT_CLK_DIV + 1" -# ] [ipgui::get_guiparamspec -name "DEFAULT_CLK_DIV" -component $cc] -# set mosi_miso_config_group [ipgui::add_group -name "MOSI/MISO Configuration" -component $cc \ -# -parent $page0 -display_name "MOSI/MISO Configuration" ] -# ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $mosi_miso_config_group -WARNING: [IP_Flow 19-465] param 'NUM_OF_SDI' already exists. Ignoring. -# set_property -dict [list \ -# "display_name" "Number of MISO" \ -# "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" -# ] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] -# ipgui::add_param -name "SDI_DELAY" -component $cc -parent $mosi_miso_config_group -# set_property -dict [list \ -# "display_name" "Delay MISO latching" \ -# "tooltip" "\[SDI_DELAY\] Delay the MISO latching to the next consecutive SCLK edge" -# ] [ipgui::get_guiparamspec -name "SDI_DELAY" -component $cc] -# ipgui::add_param -name "SDO_DEFAULT" -component $cc -parent $mosi_miso_config_group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "MOSI default level" \ -# "tooltip" "\[SDO_DEFAULT\] Define the default voltage level on MOSI" -# ] [ipgui::get_guiparamspec -name "SDO_DEFAULT" -component $cc] -# ipx::create_xgui_files $cc -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:07:50 2021... diff --git a/adi_library/spi_engine/spi_engine_execution/vivado.jou b/adi_library/spi_engine/spi_engine_execution/vivado.jou deleted file mode 100644 index 64944deb..00000000 --- a/adi_library/spi_engine/spi_engine_execution/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:07:43 2021 -# Process ID: 3259 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution -# Command line: vivado -mode batch -source spi_engine_execution_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution/vivado.jou -#----------------------------------------------------------- -source spi_engine_execution_ip.tcl diff --git a/adi_library/spi_engine/spi_engine_execution/vivado.log b/adi_library/spi_engine/spi_engine_execution/vivado.log deleted file mode 100644 index da02b5a2..00000000 --- a/adi_library/spi_engine/spi_engine_execution/vivado.log +++ /dev/null @@ -1,973 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:07:43 2021 -# Process ID: 3259 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution -# Command line: vivado -mode batch -source spi_engine_execution_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution/vivado.jou -#----------------------------------------------------------- -source spi_engine_execution_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create spi_engine_execution -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files spi_engine_execution [list \ -# "spi_engine_execution.v" \ -# ] -# adi_ip_properties_lite spi_engine_execution -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter2' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter2' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'bit_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'transfer_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'transfer_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_transfer_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_TRANSFER'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_write_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_WRITE'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_chipselect_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_CHIPSELECT'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_misc_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_MISC'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_sync_cmd' has a dependency on the module local parameter or undefined parameter 'MISC_SYNC'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_active_s' has a dependency on the module local parameter or undefined parameter 'CMD_CHIPSELECT'. -INFO: [IP_Flow 19-4821] For module 'spi_engine_execution', parameter 'SDO_DEFAULT' is inferred to be bitString format. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'interface_jesd204_tx_status'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_0' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_1' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_2' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_3' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_4' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_5' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_6' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_7' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_EN on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLE on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port MEM_RESET on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLED on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SYNC_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_spi_engine_offload_ctrl' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_spi_master' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_DATA on bus interface abstraction spi_engine_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SDO_READY on bus interface abstraction spi_engine_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SDO_VALID on bus interface abstraction spi_engine_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SDI_READY on bus interface abstraction spi_engine_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SDI_VALID on bus interface abstraction spi_engine_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SYNC_DATA on bus interface abstraction spi_engine_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_spi_engine_ctrl' of definition 'analog.com:interface:spi_engine_ctrl:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_valid' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data_ready' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_0': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_1': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_2': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_3': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_4': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_5': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_6': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_7': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "ENABLE" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "CMD_DATA" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDO_READY" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDO_VALID" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDI_READY" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDI_VALID" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# adi_add_bus "ctrl" "slave" \ -# "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_ctrl:1.0" \ -# { -# {"cmd_ready" "CMD_READY"} \ -# {"cmd_valid" "CMD_VALID"} \ -# {"cmd" "CMD_DATA"} \ -# {"sdo_data_ready" "SDO_READY"} \ -# {"sdo_data_valid" "SDO_VALID"} \ -# {"sdo_data" "SDO_DATA"} \ -# {"sdi_data_ready" "SDI_READY"} \ -# {"sdi_data_valid" "SDI_VALID"} \ -# {"sdi_data" "SDI_DATA"} \ -# {"sync_ready" "SYNC_READY"} \ -# {"sync_valid" "SYNC_VALID"} \ -# {"sync" "SYNC_DATA"} \ -# } -# adi_add_bus_clock "clk" "ctrl" "resetn" -# adi_add_bus "spi" "master" \ -# "analog.com:interface:spi_master_rtl:1.0" \ -# "analog.com:interface:spi_master:1.0" \ -# { -# {"sclk" "SCLK"} \ -# {"sdi" "SDI"} \ -# {"sdo" "SDO"} \ -# {"sdo_t" "SDO_T"} \ -# {"three_wire" "THREE_WIRE"} \ -# {"cs" "CS"} \ -# } -# adi_add_bus_clock "clk" "spi" "resetn" -# set cc [ipx::current_core] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "8" \ -# "value_validation_range_maximum" "256" \ -# ] \ -# [ipx::get_user_parameters DATA_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "32" \ -# ] \ -# [ipx::get_user_parameters NUM_OF_CS -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "8" \ -# ] \ -# [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_list" "0 1 2 3" \ -# ] \ -# [ipx::get_user_parameters DEFAULT_SPI_CFG -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_range_minimum" "0" \ -# "value_validation_range_maximum" "255" \ -# ] \ -# [ipx::get_user_parameters DEFAULT_CLK_DIV -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "list" \ -# "value_validation_list" "0 1" \ -# ] \ -# [ipx::get_user_parameters SDO_DEFAULT -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_user_parameters SDI_DELAY -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_hdl_parameters SDI_DELAY -of_objects $cc] -# ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] -# ipx::save_core [ipx::current_core] -# ipgui::add_page -name {SPI Engine execution} -component [ipx::current_core] -display_name {AXI SPI Engine execution} -# set page0 [ipgui::get_pagespec -name "SPI Engine execution" -component $cc] -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration" ] -# ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Parallel data width" \ -# "tooltip" "\[DATA_WIDTH\] Define the data interface width" -# ] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] -# ipgui::add_param -name "NUM_OF_CS" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Number of CSN lines" \ -# "tooltip" "\[NUM_OF_CS\] Define the number of chip select lines" \ -# ] [ipgui::get_guiparamspec -name "NUM_OF_CS" -component $cc] -# ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Number of MISO lines" \ -# "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ -# ] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] -# set spi_config_group [ipgui::add_group -name "SPI Configuration" -component $cc \ -# -parent $page0 -display_name "SPI Configuration" ] -# ipgui::add_param -name "DEFAULT_SPI_CFG" -component $cc -parent $spi_config_group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "Default SPI mode" \ -# "tooltip" "\[DEFAULT_SPI_CFG\] Define the default SPI configuration, bit 1 defines CPOL, bit 0 defines CPHA" -# ] [ipgui::get_guiparamspec -name "DEFAULT_SPI_CFG" -component $cc] -# ipgui::add_param -name "DEFAULT_CLK_DIV" -component $cc -parent $spi_config_group -# set_property -dict [list \ -# "display_name" "Default SCLK divider" \ -# "tooltip" "\[DEFAULT_CLK_DIV\] Define the default SCLK divider, fSCLK = fCoreClk / DEFAULT_CLK_DIV + 1" -# ] [ipgui::get_guiparamspec -name "DEFAULT_CLK_DIV" -component $cc] -# set mosi_miso_config_group [ipgui::add_group -name "MOSI/MISO Configuration" -component $cc \ -# -parent $page0 -display_name "MOSI/MISO Configuration" ] -# ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $mosi_miso_config_group -WARNING: [IP_Flow 19-465] param 'NUM_OF_SDI' already exists. Ignoring. -# set_property -dict [list \ -# "display_name" "Number of MISO" \ -# "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" -# ] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] -# ipgui::add_param -name "SDI_DELAY" -component $cc -parent $mosi_miso_config_group -# set_property -dict [list \ -# "display_name" "Delay MISO latching" \ -# "tooltip" "\[SDI_DELAY\] Delay the MISO latching to the next consecutive SCLK edge" -# ] [ipgui::get_guiparamspec -name "SDI_DELAY" -component $cc] -# ipgui::add_param -name "SDO_DEFAULT" -component $cc -parent $mosi_miso_config_group -# set_property -dict [list \ -# "widget" "comboBox" \ -# "display_name" "MOSI default level" \ -# "tooltip" "\[SDO_DEFAULT\] Define the default voltage level on MOSI" -# ] [ipgui::get_guiparamspec -name "SDO_DEFAULT" -component $cc] -# ipx::create_xgui_files $cc -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:07:50 2021... diff --git a/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.log b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.log deleted file mode 100644 index 7c013c50..00000000 --- a/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.log +++ /dev/null @@ -1,1312 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source spi_engine_interconnect_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create spi_engine_interconnect -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_interconnect'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files spi_engine_interconnect [list \ -# "spi_engine_interconnect.v" \ -# ] -# adi_ip_properties_lite spi_engine_interconnect -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'm'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'm_cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'm_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'm_sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 's0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 's0_cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 's0_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 's0_sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 's1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 's1_cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 's1_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 's1_sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_sdo' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_sdo' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_sdo' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'm'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 's0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 's1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'm_cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'm_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'm_sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 's0_cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 's0_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 's0_sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 's1_cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 's1_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 's1_sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port CMD_WR_EN on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port CMD_WR_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ENABLE on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port MEM_RESET on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ENABLED on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port SYNC_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_EN on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLE on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port MEM_RESET on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLED on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SYNC_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_EN on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLE on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port MEM_RESET on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLED on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SYNC_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port SCLK on bus interface abstraction spi_master_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port CS on bus interface abstraction spi_master_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_data' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port SCLK on bus interface abstraction spi_master_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port CS on bus interface abstraction spi_master_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_data' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port SCLK on bus interface abstraction spi_master_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port CS on bus interface abstraction spi_master_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_data' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_4': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_5': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_6': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_7': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_sync_ready' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_ready': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_sdo': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_valid': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_4': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_5': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_6': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_7': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_ready': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sdi_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_sdo': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync_valid' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_valid': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_4': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_5': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_6': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_7': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_ready': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sdi_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_sdo': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync_valid' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_valid': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_sync_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_sync': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_cmd_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_sync': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_cmd_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_sync': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_sync_ready' and definition port 'SYNC_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_sync_valid' and definition port 'SYNC_VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm': A port map to the required logical port "ENABLE" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0': A port map to the required logical port "ENABLE" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1': A port map to the required logical port "ENABLE" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_sdi_data' and definition port 'SDI'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_sdo_data' and definition port 'SDO'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_data': A port map to the required logical port "SCLK" of the bus abstraction "analog.com:interface:spi_master_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_data': A port map to the required logical port "CS" of the bus abstraction "analog.com:interface:spi_master_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_data': A port map to the required logical port "SCLK" of the bus abstraction "analog.com:interface:spi_master_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_data': A port map to the required logical port "CS" of the bus abstraction "analog.com:interface:spi_master_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_data': A port map to the required logical port "SCLK" of the bus abstraction "analog.com:interface:spi_master_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_data': A port map to the required logical port "CS" of the bus abstraction "analog.com:interface:spi_master_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# adi_add_bus "m_ctrl" "master" \ -# "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_ctrl:1.0" \ -# { \ -# {"m_cmd_ready" "CMD_READY"} \ -# {"m_cmd_valid" "CMD_VALID"} \ -# {"m_cmd_data" "CMD_DATA"} \ -# {"m_sdo_ready" "SDO_READY"} \ -# {"m_sdo_valid" "SDO_VALID"} \ -# {"m_sdo_data" "SDO_DATA"} \ -# {"m_sdi_ready" "SDI_READY"} \ -# {"m_sdi_valid" "SDI_VALID"} \ -# {"m_sdi_data" "SDI_DATA"} \ -# {"m_sync_ready" "SYNC_READY"} \ -# {"m_sync_valid" "SYNC_VALID"} \ -# {"m_sync" "SYNC_DATA"} \ -# } -# adi_add_bus_clock "clk" "m_ctrl" "resetn" -# foreach prefix [list "s0" "s1"] { -# adi_add_bus [format "%s_ctrl" $prefix] "slave" \ -# "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_ctrl:1.0" \ -# [list \ -# [list [format "%s_cmd_ready" $prefix] "CMD_READY"] \ -# [list [format "%s_cmd_valid" $prefix] "CMD_VALID"] \ -# [list [format "%s_cmd_data" $prefix] "CMD_DATA"] \ -# [list [format "%s_sdo_ready" $prefix] "SDO_READY"] \ -# [list [format "%s_sdo_valid" $prefix] "SDO_VALID"] \ -# [list [format "%s_sdo_data" $prefix] "SDO_DATA"] \ -# [list [format "%s_sdi_ready" $prefix] "SDI_READY"] \ -# [list [format "%s_sdi_valid" $prefix] "SDI_VALID"] \ -# [list [format "%s_sdi_data" $prefix] "SDI_DATA"] \ -# [list [format "%s_sync_ready" $prefix] "SYNC_READY"] \ -# [list [format "%s_sync_valid" $prefix] "SYNC_VALID"] \ -# [list [format "%s_sync" $prefix] "SYNC_DATA"] \ -# ] -# adi_add_bus_clock "clk" [format "%s_ctrl" $prefix] "resetn" -# } -# set cc [ipx::current_core] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "8" \ -# "value_validation_range_maximum" "256" \ -# ] \ -# [ipx::get_user_parameters DATA_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "8" \ -# ] \ -# [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] -# ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] -# ipx::save_core [ipx::current_core] -# ipgui::add_page -name {SPI Engine interconnect} -component [ipx::current_core] -display_name {SPI Engine interconnect} -# set page0 [ipgui::get_pagespec -name "SPI Engine interconnect" -component $cc] -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration" ] -# ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Parallel data width" \ -# "tooltip" "\[DATA_WIDTH\] Define the data interface width" -# ] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] -# ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Number of MISO lines" \ -# "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ -# ] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] -# ipx::create_xgui_files $cc -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:07:57 2021... diff --git a/adi_library/spi_engine/spi_engine_interconnect/vivado.jou b/adi_library/spi_engine/spi_engine_interconnect/vivado.jou deleted file mode 100644 index f83c5b40..00000000 --- a/adi_library/spi_engine/spi_engine_interconnect/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:07:50 2021 -# Process ID: 3311 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_interconnect -# Command line: vivado -mode batch -source spi_engine_interconnect_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_interconnect/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_interconnect/vivado.jou -#----------------------------------------------------------- -source spi_engine_interconnect_ip.tcl diff --git a/adi_library/spi_engine/spi_engine_interconnect/vivado.log b/adi_library/spi_engine/spi_engine_interconnect/vivado.log deleted file mode 100644 index a19044a4..00000000 --- a/adi_library/spi_engine/spi_engine_interconnect/vivado.log +++ /dev/null @@ -1,1317 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:07:50 2021 -# Process ID: 3311 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_interconnect -# Command line: vivado -mode batch -source spi_engine_interconnect_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_interconnect/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_interconnect/vivado.jou -#----------------------------------------------------------- -source spi_engine_interconnect_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create spi_engine_interconnect -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_interconnect'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files spi_engine_interconnect [list \ -# "spi_engine_interconnect.v" \ -# ] -# adi_ip_properties_lite spi_engine_interconnect -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'm'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'm_cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'm_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'm_sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 's0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 's0_cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 's0_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 's0_sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 's1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 's1_cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 's1_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 's1_sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_sdo' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_sdo' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_sdo' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_cmd' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_cmd' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_cmd' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'm'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 's0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 's1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'm_cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'm_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'm_sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 's0_cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 's0_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 's0_sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 's1_cmd'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 's1_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 's1_sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port CMD_WR_EN on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port CMD_WR_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ENABLE on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port MEM_RESET on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ENABLED on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port SYNC_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_EN on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLE on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port MEM_RESET on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLED on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SYNC_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_EN on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLE on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port MEM_RESET on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLED on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port SYNC_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port SCLK on bus interface abstraction spi_master_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port CS on bus interface abstraction spi_master_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_data' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port SCLK on bus interface abstraction spi_master_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port CS on bus interface abstraction spi_master_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's0_data' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port SCLK on bus interface abstraction spi_master_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port CS on bus interface abstraction spi_master_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's1_data' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_4': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_5': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_6': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_7': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_sync_ready' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_ready': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_sdo': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_valid': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_4': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_5': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_6': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_7': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_ready': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sdi_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_sdo': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_sync_valid' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_valid': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_4': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_5': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_6': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_7': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_ready': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sdi_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_sdo': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_sync_valid' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_valid': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_sync_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_sync': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's0_cmd_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_sync': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_cmd_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's1_cmd_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_sync': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_sync_ready' and definition port 'SYNC_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_sync_valid' and definition port 'SYNC_VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm': A port map to the required logical port "ENABLE" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0': A port map to the required logical port "ENABLE" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1': A port map to the required logical port "ENABLE" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_sdi_data' and definition port 'SDI'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_sdo_data' and definition port 'SDO'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_data': A port map to the required logical port "SCLK" of the bus abstraction "analog.com:interface:spi_master_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_data': A port map to the required logical port "CS" of the bus abstraction "analog.com:interface:spi_master_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_data': A port map to the required logical port "SCLK" of the bus abstraction "analog.com:interface:spi_master_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's0_data': A port map to the required logical port "CS" of the bus abstraction "analog.com:interface:spi_master_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_data': A port map to the required logical port "SCLK" of the bus abstraction "analog.com:interface:spi_master_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's1_data': A port map to the required logical port "CS" of the bus abstraction "analog.com:interface:spi_master_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# adi_add_bus "m_ctrl" "master" \ -# "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_ctrl:1.0" \ -# { \ -# {"m_cmd_ready" "CMD_READY"} \ -# {"m_cmd_valid" "CMD_VALID"} \ -# {"m_cmd_data" "CMD_DATA"} \ -# {"m_sdo_ready" "SDO_READY"} \ -# {"m_sdo_valid" "SDO_VALID"} \ -# {"m_sdo_data" "SDO_DATA"} \ -# {"m_sdi_ready" "SDI_READY"} \ -# {"m_sdi_valid" "SDI_VALID"} \ -# {"m_sdi_data" "SDI_DATA"} \ -# {"m_sync_ready" "SYNC_READY"} \ -# {"m_sync_valid" "SYNC_VALID"} \ -# {"m_sync" "SYNC_DATA"} \ -# } -# adi_add_bus_clock "clk" "m_ctrl" "resetn" -# foreach prefix [list "s0" "s1"] { -# adi_add_bus [format "%s_ctrl" $prefix] "slave" \ -# "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_ctrl:1.0" \ -# [list \ -# [list [format "%s_cmd_ready" $prefix] "CMD_READY"] \ -# [list [format "%s_cmd_valid" $prefix] "CMD_VALID"] \ -# [list [format "%s_cmd_data" $prefix] "CMD_DATA"] \ -# [list [format "%s_sdo_ready" $prefix] "SDO_READY"] \ -# [list [format "%s_sdo_valid" $prefix] "SDO_VALID"] \ -# [list [format "%s_sdo_data" $prefix] "SDO_DATA"] \ -# [list [format "%s_sdi_ready" $prefix] "SDI_READY"] \ -# [list [format "%s_sdi_valid" $prefix] "SDI_VALID"] \ -# [list [format "%s_sdi_data" $prefix] "SDI_DATA"] \ -# [list [format "%s_sync_ready" $prefix] "SYNC_READY"] \ -# [list [format "%s_sync_valid" $prefix] "SYNC_VALID"] \ -# [list [format "%s_sync" $prefix] "SYNC_DATA"] \ -# ] -# adi_add_bus_clock "clk" [format "%s_ctrl" $prefix] "resetn" -# } -# set cc [ipx::current_core] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "8" \ -# "value_validation_range_maximum" "256" \ -# ] \ -# [ipx::get_user_parameters DATA_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "8" \ -# ] \ -# [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] -# ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] -# ipx::save_core [ipx::current_core] -# ipgui::add_page -name {SPI Engine interconnect} -component [ipx::current_core] -display_name {SPI Engine interconnect} -# set page0 [ipgui::get_pagespec -name "SPI Engine interconnect" -component $cc] -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration" ] -# ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Parallel data width" \ -# "tooltip" "\[DATA_WIDTH\] Define the data interface width" -# ] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] -# ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Number of MISO lines" \ -# "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ -# ] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] -# ipx::create_xgui_files $cc -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:07:57 2021... diff --git a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_ip.log b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_ip.log deleted file mode 100644 index afcb8c35..00000000 --- a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_ip.log +++ /dev/null @@ -1,1193 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source spi_engine_offload_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create spi_engine_offload -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_offload'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files spi_engine_offload [list \ -# "spi_engine_offload_constr.ttcl" \ -# "spi_engine_offload.v" \ -# ] -# adi_ip_properties_lite spi_engine_offload -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_offload/spi_engine_offload_constr.ttcl' ignored by IP packager. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'offload_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'status_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'status_sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_sdo_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'ctrl_sdo_data'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'ctrl_sdo_data'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'status_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_wr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'ctrl_sdo_wr'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'offload_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'status_sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_10' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_11' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_12' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_13' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_14' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_15' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_4' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_5' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_6' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_7' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_8' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_9' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_wr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'ctrl_sdo_wr'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_EN on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLE on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port MEM_RESET on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLED on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'ctrl_wr_data'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'offload_data'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port CMD_DATA on bus interface abstraction spi_engine_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port SDO_READY on bus interface abstraction spi_engine_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port SDO_VALID on bus interface abstraction spi_engine_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload' of definition 'analog.com:interface:spi_engine_ctrl:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'spi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'spi_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'spi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'spi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'spi_resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'offload_sdi_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_ready' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data_valid' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_4': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_5': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_6': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_7': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_ready': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_valid' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_valid': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_12': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_13': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_14': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_15': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_ready' and definition port 'SYNC_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_valid' and definition port 'SYNC_VALID'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_data' and definition port 'SYNC_DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "ENABLE" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_ready' and definition port 'CMD_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_valid' and definition port 'CMD_VALID'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'SDO_DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_ready' and definition port 'SYNC_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_valid' and definition port 'SYNC_VALID'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_data' and definition port 'SYNC_DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "CMD_DATA" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "SDO_READY" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "SDO_VALID" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ctrl_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'spi_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_ttcl axi_spi_engine "spi_engine_offload_constr.ttcl" -# ipx::remove_all_bus_interface [ipx::current_core] -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# } -# adi_add_bus "spi_engine_ctrl" "master" \ -# "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_ctrl:1.0" \ -# { -# {"cmd_ready" "CMD_READY"} \ -# {"cmd_valid" "CMD_VALID"} \ -# {"cmd" "CMD_DATA"} \ -# {"sdo_data_ready" "SDO_READY"} \ -# {"sdo_data_valid" "SDO_VALID"} \ -# {"sdo_data" "SDO_DATA"} \ -# {"sdi_data_ready" "SDI_READY"} \ -# {"sdi_data_valid" "SDI_VALID"} \ -# {"sdi_data" "SDI_DATA"} \ -# {"sync_ready" "SYNC_READY"} \ -# {"sync_valid" "SYNC_VALID"} \ -# {"sync_data" "SYNC_DATA"} \ -# } -# adi_add_bus "spi_engine_offload_ctrl" "slave" \ -# "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_offload_ctrl:1.0" \ -# { \ -# { "ctrl_cmd_wr_en" "CMD_WR_EN"} \ -# { "ctrl_cmd_wr_data" "CMD_WR_DATA"} \ -# { "ctrl_sdo_wr_en" "SDO_WR_EN"} \ -# { "ctrl_sdo_wr_data" "SDO_WR_DATA"} \ -# { "ctrl_enable" "ENABLE"} \ -# { "ctrl_enabled" "ENABLED"} \ -# { "ctrl_mem_reset" "MEM_RESET"} \ -# { "status_sync_ready" "SYNC_READY"} \ -# { "status_sync_valid" "SYNC_VALID"} \ -# { "status_sync_data" "SYNC_DATA"} \ -# } -# adi_add_bus "offload_sdi" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { \ -# {"offload_sdi_valid" "TVALID"} \ -# {"offload_sdi_ready" "TREADY"} \ -# {"offload_sdi_data" "TDATA"} \ -# } -# adi_add_bus_clock "spi_clk" "spi_engine_ctrl:offload_sdi" "spi_resetn" -# adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl" -# set cc [ipx::current_core] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_user_parameters ASYNC_SPI_CLK -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_hdl_parameters ASYNC_SPI_CLK -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_user_parameters ASYNC_TRIG -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_hdl_parameters ASYNC_TRIG -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "8" \ -# ] \ -# [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "8" \ -# "value_validation_range_maximum" "256" \ -# ] \ -# [ipx::get_user_parameters DATA_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters CMD_MEM_ADDRESS_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters SDO_MEM_ADDRESS_WIDTH -of_objects $cc] -# ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] -# ipx::save_core [ipx::current_core] -# ipgui::add_page -name {SPI Engine RX offload} -component [ipx::current_core] -display_name {SPI Engine RX offload} -# set page0 [ipgui::get_pagespec -name "SPI Engine RX offload" -component $cc] -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration" ] -# ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Shift register's data width" \ -# "tooltip" "\[DATA_WIDTH\] Define the data interface width" -# ] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] -# ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Number of MISO lines" \ -# "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ -# ] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] -# ipgui::add_param -name "ASYNC_SPI_CLK" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Asynchronous core clock" \ -# "tooltip" "\[ASYNC_SPI_CLK\] Define the relationship between the core clock and the memory mapped interface clock" \ -# ] [ipgui::get_guiparamspec -name "ASYNC_SPI_CLK" -component $cc] -# ipgui::add_param -name "ASYNC_TRIG" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Asynchronous trigger" \ -# "tooltip" "\[ASYNC_TRIG\] Set if the external trigger is asynchronous to the core clk" \ -# ] [ipgui::get_guiparamspec -name "ASYNC_TRIG" -component $cc] -# set cmd_stream_fifo_group [ipgui::add_group -name "Command stream FIFO configuration" -component $cc \ -# -parent $page0 -display_name "Command stream FIFO configuration" ] -# ipgui::add_param -name "CMD_MEM_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group -# set_property -dict [list \ -# "display_name" "Command FIFO address width" \ -# "tooltip" "\[CMD_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "CMD_MEM_ADDRESS_WIDTH" -component $cc] -# ipgui::add_param -name "SDO_MEM_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group -# set_property -dict [list \ -# "display_name" "MOSI FIFO address width" \ -# "tooltip" "\[SDO_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "SDO_MEM_ADDRESS_WIDTH" -component $cc] -# ipx::create_xgui_files $cc -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:08:04 2021... diff --git a/adi_library/spi_engine/spi_engine_offload/vivado.jou b/adi_library/spi_engine/spi_engine_offload/vivado.jou deleted file mode 100644 index e0591c98..00000000 --- a/adi_library/spi_engine/spi_engine_offload/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:07:58 2021 -# Process ID: 3367 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_offload -# Command line: vivado -mode batch -source spi_engine_offload_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_offload/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_offload/vivado.jou -#----------------------------------------------------------- -source spi_engine_offload_ip.tcl diff --git a/adi_library/spi_engine/spi_engine_offload/vivado.log b/adi_library/spi_engine/spi_engine_offload/vivado.log deleted file mode 100644 index 5cc485f2..00000000 --- a/adi_library/spi_engine/spi_engine_offload/vivado.log +++ /dev/null @@ -1,1198 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:07:58 2021 -# Process ID: 3367 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_offload -# Command line: vivado -mode batch -source spi_engine_offload_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_offload/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_offload/vivado.jou -#----------------------------------------------------------- -source spi_engine_offload_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create spi_engine_offload -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_offload'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files spi_engine_offload [list \ -# "spi_engine_offload_constr.ttcl" \ -# "spi_engine_offload.v" \ -# ] -# adi_ip_properties_lite spi_engine_offload -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_offload/spi_engine_offload_constr.ttcl' ignored by IP packager. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'offload_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'status_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'status_sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_sdo_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload_sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_data_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'ctrl_sdo_data'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status_sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'ctrl_sdo_data'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'status_data'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_wr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'ctrl_sdo_wr'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'offload_sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'status_sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'sync'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_10' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_11' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_12' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_13' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_14' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_15' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_4' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_5' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_6' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_7' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_8' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port rd on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_cmd_wr_9' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'ctrl_cmd_wr'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'ctrl_sdo_wr'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_EN on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLE on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port MEM_RESET on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLED on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'status' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'ctrl_wr_data'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'offload_data'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port CMD_DATA on bus interface abstraction spi_engine_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port SDO_READY on bus interface abstraction spi_engine_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port SDO_VALID on bus interface abstraction spi_engine_ctrl_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'offload' of definition 'analog.com:interface:spi_engine_ctrl:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'spi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'spi_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'spi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'spi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'spi_resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'offload_sdi_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload_sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_ready' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data_valid' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_4': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_5': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_6': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_7': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_data_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_ready': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync_valid' and definition port 'SYNC'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_valid': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status_sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_12': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_13': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_14': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_15': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ctrl_cmd_wr_data' and definition port 'data'. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_cmd_wr_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_ready' and definition port 'SYNC_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_valid' and definition port 'SYNC_VALID'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_data' and definition port 'SYNC_DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "ENABLE" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_ready' and definition port 'CMD_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_valid' and definition port 'CMD_VALID'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data' and definition port 'SDO_DATA'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_ready' and definition port 'SYNC_READY'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_valid' and definition port 'SYNC_VALID'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync_data' and definition port 'SYNC_DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "CMD_DATA" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "SDO_READY" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'offload': A port map to the required logical port "SDO_VALID" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ctrl_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'spi_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_ttcl axi_spi_engine "spi_engine_offload_constr.ttcl" -# ipx::remove_all_bus_interface [ipx::current_core] -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# } -# adi_add_bus "spi_engine_ctrl" "master" \ -# "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_ctrl:1.0" \ -# { -# {"cmd_ready" "CMD_READY"} \ -# {"cmd_valid" "CMD_VALID"} \ -# {"cmd" "CMD_DATA"} \ -# {"sdo_data_ready" "SDO_READY"} \ -# {"sdo_data_valid" "SDO_VALID"} \ -# {"sdo_data" "SDO_DATA"} \ -# {"sdi_data_ready" "SDI_READY"} \ -# {"sdi_data_valid" "SDI_VALID"} \ -# {"sdi_data" "SDI_DATA"} \ -# {"sync_ready" "SYNC_READY"} \ -# {"sync_valid" "SYNC_VALID"} \ -# {"sync_data" "SYNC_DATA"} \ -# } -# adi_add_bus "spi_engine_offload_ctrl" "slave" \ -# "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \ -# "analog.com:interface:spi_engine_offload_ctrl:1.0" \ -# { \ -# { "ctrl_cmd_wr_en" "CMD_WR_EN"} \ -# { "ctrl_cmd_wr_data" "CMD_WR_DATA"} \ -# { "ctrl_sdo_wr_en" "SDO_WR_EN"} \ -# { "ctrl_sdo_wr_data" "SDO_WR_DATA"} \ -# { "ctrl_enable" "ENABLE"} \ -# { "ctrl_enabled" "ENABLED"} \ -# { "ctrl_mem_reset" "MEM_RESET"} \ -# { "status_sync_ready" "SYNC_READY"} \ -# { "status_sync_valid" "SYNC_VALID"} \ -# { "status_sync_data" "SYNC_DATA"} \ -# } -# adi_add_bus "offload_sdi" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { \ -# {"offload_sdi_valid" "TVALID"} \ -# {"offload_sdi_ready" "TREADY"} \ -# {"offload_sdi_data" "TDATA"} \ -# } -# adi_add_bus_clock "spi_clk" "spi_engine_ctrl:offload_sdi" "spi_resetn" -# adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl" -# set cc [ipx::current_core] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_user_parameters ASYNC_SPI_CLK -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_hdl_parameters ASYNC_SPI_CLK -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_user_parameters ASYNC_TRIG -of_objects $cc] -# set_property -dict [list \ -# "value_format" "bool" \ -# "value" "false" \ -# ] \ -# [ipx::get_hdl_parameters ASYNC_TRIG -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "8" \ -# ] \ -# [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "8" \ -# "value_validation_range_maximum" "256" \ -# ] \ -# [ipx::get_user_parameters DATA_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters CMD_MEM_ADDRESS_WIDTH -of_objects $cc] -# set_property -dict [list \ -# "value_validation_type" "range_long" \ -# "value_validation_range_minimum" "1" \ -# "value_validation_range_maximum" "16" \ -# ] \ -# [ipx::get_user_parameters SDO_MEM_ADDRESS_WIDTH -of_objects $cc] -# ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] -# ipx::save_core [ipx::current_core] -# ipgui::add_page -name {SPI Engine RX offload} -component [ipx::current_core] -display_name {SPI Engine RX offload} -# set page0 [ipgui::get_pagespec -name "SPI Engine RX offload" -component $cc] -# set general_group [ipgui::add_group -name "General Configuration" -component $cc \ -# -parent $page0 -display_name "General Configuration" ] -# ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Shift register's data width" \ -# "tooltip" "\[DATA_WIDTH\] Define the data interface width" -# ] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] -# ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Number of MISO lines" \ -# "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ -# ] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] -# ipgui::add_param -name "ASYNC_SPI_CLK" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Asynchronous core clock" \ -# "tooltip" "\[ASYNC_SPI_CLK\] Define the relationship between the core clock and the memory mapped interface clock" \ -# ] [ipgui::get_guiparamspec -name "ASYNC_SPI_CLK" -component $cc] -# ipgui::add_param -name "ASYNC_TRIG" -component $cc -parent $general_group -# set_property -dict [list \ -# "display_name" "Asynchronous trigger" \ -# "tooltip" "\[ASYNC_TRIG\] Set if the external trigger is asynchronous to the core clk" \ -# ] [ipgui::get_guiparamspec -name "ASYNC_TRIG" -component $cc] -# set cmd_stream_fifo_group [ipgui::add_group -name "Command stream FIFO configuration" -component $cc \ -# -parent $page0 -display_name "Command stream FIFO configuration" ] -# ipgui::add_param -name "CMD_MEM_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group -# set_property -dict [list \ -# "display_name" "Command FIFO address width" \ -# "tooltip" "\[CMD_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "CMD_MEM_ADDRESS_WIDTH" -component $cc] -# ipgui::add_param -name "SDO_MEM_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group -# set_property -dict [list \ -# "display_name" "MOSI FIFO address width" \ -# "tooltip" "\[SDO_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \ -# ] [ipgui::get_guiparamspec -name "SDO_MEM_ADDRESS_WIDTH" -component $cc] -# ipx::create_xgui_files $cc -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:08:04 2021... diff --git a/adi_library/sysid_rom/sysid_rom_ip.log b/adi_library/sysid_rom/sysid_rom_ip.log deleted file mode 100644 index 936d721d..00000000 --- a/adi_library/sysid_rom/sysid_rom_ip.log +++ /dev/null @@ -1,692 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source sysid_rom_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create sysid_rom -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/sysid_rom'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files sysid_rom [list \ -# "sysid_rom.v"] -# adi_ip_properties_lite sysid_rom -WARNING: [IP_Flow 19-5150] The Range '(ROM_WIDTH - 1):0' is present in all ports of the interface 'rom'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rom' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(ROM_WIDTH - 1):0' is present in all ports of the interface 'rom'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rom_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rom': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# set cc [ipx::current_core] -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:23:43 2021... diff --git a/adi_library/sysid_rom/vivado.jou b/adi_library/sysid_rom/vivado.jou deleted file mode 100644 index 58613c10..00000000 --- a/adi_library/sysid_rom/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:23:36 2021 -# Process ID: 66891 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/sysid_rom -# Command line: vivado -mode batch -source sysid_rom_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/sysid_rom/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/sysid_rom/vivado.jou -#----------------------------------------------------------- -source sysid_rom_ip.tcl diff --git a/adi_library/sysid_rom/vivado.log b/adi_library/sysid_rom/vivado.log deleted file mode 100644 index b3764187..00000000 --- a/adi_library/sysid_rom/vivado.log +++ /dev/null @@ -1,697 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:23:36 2021 -# Process ID: 66891 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/sysid_rom -# Command line: vivado -mode batch -source sysid_rom_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/sysid_rom/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/sysid_rom/vivado.jou -#----------------------------------------------------------- -source sysid_rom_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create sysid_rom -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/sysid_rom'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files sysid_rom [list \ -# "sysid_rom.v"] -# adi_ip_properties_lite sysid_rom -WARNING: [IP_Flow 19-5150] The Range '(ROM_WIDTH - 1):0' is present in all ports of the interface 'rom'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rom' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(ROM_WIDTH - 1):0' is present in all ports of the interface 'rom'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rom_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rom': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# set cc [ipx::current_core] -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core $cc -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:23:43 2021... diff --git a/adi_library/util_adcfifo/util_adcfifo_ip.log b/adi_library/util_adcfifo/util_adcfifo_ip.log deleted file mode 100644 index 35ccfcd7..00000000 --- a/adi_library/util_adcfifo/util_adcfifo_ip.log +++ /dev/null @@ -1,727 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_adcfifo_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_adcfifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_adcfifo [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \ -# "$ad_hdl_dir/library/common/ad_mem_asym.v" \ -# "util_adcfifo.v" \ -# "util_adcfifo_constr.xdc" ] -# adi_ip_properties_lite util_adcfifo -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'adc_waddr_int' has a dependency on the module local parameter or undefined parameter 'ADC_ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dma_waddr_int_s' has a dependency on the module local parameter or undefined parameter 'ADC_ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'adc_waddr_int_s' has a dependency on the module local parameter or undefined parameter 'ADC_ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port rdata on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(ADC_DATA_WIDTH - 1):0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_xfer_req' and definition port 'XFER_REQ'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "rdata" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# } -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -# ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:55 2021... diff --git a/adi_library/util_adcfifo/vivado.jou b/adi_library/util_adcfifo/vivado.jou deleted file mode 100644 index bde0313e..00000000 --- a/adi_library/util_adcfifo/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:17:47 2021 -# Process ID: 7022 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo -# Command line: vivado -mode batch -source util_adcfifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo/vivado.jou -#----------------------------------------------------------- -source util_adcfifo_ip.tcl diff --git a/adi_library/util_adcfifo/vivado.log b/adi_library/util_adcfifo/vivado.log deleted file mode 100644 index dc3a6ab0..00000000 --- a/adi_library/util_adcfifo/vivado.log +++ /dev/null @@ -1,732 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:17:47 2021 -# Process ID: 7022 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo -# Command line: vivado -mode batch -source util_adcfifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo/vivado.jou -#----------------------------------------------------------- -source util_adcfifo_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_adcfifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_adcfifo [list \ -# "$ad_hdl_dir/library/common/ad_rst.v" \ -# "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \ -# "$ad_hdl_dir/library/common/ad_mem_asym.v" \ -# "util_adcfifo.v" \ -# "util_adcfifo_constr.xdc" ] -# adi_ip_properties_lite util_adcfifo -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'adc_waddr_int' has a dependency on the module local parameter or undefined parameter 'ADC_ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dma_waddr_int_s' has a dependency on the module local parameter or undefined parameter 'ADC_ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'adc_waddr_int_s' has a dependency on the module local parameter or undefined parameter 'ADC_ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port rdata on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(ADC_DATA_WIDTH - 1):0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_xfer_req' and definition port 'XFER_REQ'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "rdata" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# } -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -# ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:55 2021... diff --git a/adi_library/util_axis_fifo/util_axis_fifo_ip.log b/adi_library/util_axis_fifo/util_axis_fifo_ip.log deleted file mode 100644 index e735ce4f..00000000 --- a/adi_library/util_axis_fifo/util_axis_fifo_ip.log +++ /dev/null @@ -1,730 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_axis_fifo_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_axis_fifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_axis_fifo [list \ -# "address_gray.v" \ -# "address_gray_pipelined.v" \ -# "address_sync.v" \ -# "../common/ad_mem.v" \ -# "util_axis_fifo.v" \ -# ] -# adi_ip_properties_lite util_axis_fifo -WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo/address_gray.v'. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'm_axis'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 's_axis'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_axis_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axis_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'm_axis_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axis_aclk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# } -# adi_add_bus "s_axis" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"s_axis_valid" "TVALID"} \ -# {"s_axis_ready" "TREADY"} \ -# {"s_axis_data" "TDATA"} \ -# } -# adi_add_bus "m_axis" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"m_axis_valid" "TVALID"} \ -# {"m_axis_ready" "TREADY"} \ -# {"m_axis_data" "TDATA"} \ -# } -# adi_add_bus_clock "m_axis_aclk" "m_axis" "m_axis_aresetn" -# adi_add_bus_clock "s_axis_aclk" "s_axis" "m_axis_aresetn" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:22:35 2021... diff --git a/adi_library/util_axis_fifo/vivado.jou b/adi_library/util_axis_fifo/vivado.jou deleted file mode 100644 index 3735b2ed..00000000 --- a/adi_library/util_axis_fifo/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:22:25 2021 -# Process ID: 66500 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo -# Command line: vivado -mode batch -source util_axis_fifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo/vivado.jou -#----------------------------------------------------------- -source util_axis_fifo_ip.tcl diff --git a/adi_library/util_axis_fifo/vivado.log b/adi_library/util_axis_fifo/vivado.log deleted file mode 100644 index fe692c94..00000000 --- a/adi_library/util_axis_fifo/vivado.log +++ /dev/null @@ -1,735 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:22:25 2021 -# Process ID: 66500 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo -# Command line: vivado -mode batch -source util_axis_fifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo/vivado.jou -#----------------------------------------------------------- -source util_axis_fifo_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_axis_fifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_axis_fifo [list \ -# "address_gray.v" \ -# "address_gray_pipelined.v" \ -# "address_sync.v" \ -# "../common/ad_mem.v" \ -# "util_axis_fifo.v" \ -# ] -# adi_ip_properties_lite util_axis_fifo -WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo/address_gray.v'. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'm_axis'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 's_axis'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_axis_aresetn'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axis_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'm_axis_aclk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 's_axis_aclk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_add_core_dependencies { \ -# analog.com:user:util_cdc:1.0 \ -# } -# adi_add_bus "s_axis" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"s_axis_valid" "TVALID"} \ -# {"s_axis_ready" "TREADY"} \ -# {"s_axis_data" "TDATA"} \ -# } -# adi_add_bus "m_axis" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"m_axis_valid" "TVALID"} \ -# {"m_axis_ready" "TREADY"} \ -# {"m_axis_data" "TDATA"} \ -# } -# adi_add_bus_clock "m_axis_aclk" "m_axis" "m_axis_aresetn" -# adi_add_bus_clock "s_axis_aclk" "s_axis" "m_axis_aresetn" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:22:35 2021... diff --git a/adi_library/util_axis_resize/util_axis_resize_ip.log b/adi_library/util_axis_resize/util_axis_resize_ip.log deleted file mode 100644 index 52fb5223..00000000 --- a/adi_library/util_axis_resize/util_axis_resize_ip.log +++ /dev/null @@ -1,717 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_axis_resize_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_axis_resize -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_resize'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_axis_resize [list \ -# "util_axis_resize.v" ] -# adi_ip_properties_lite util_axis_resize -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'count' has a dependency on the module local parameter or undefined parameter 'RATIO'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'count' has a dependency on the module local parameter or undefined parameter 'RATIO'. -WARNING: [IP_Flow 19-5150] The Range '(MASTER_DATA_WIDTH - 1):0' is present in all ports of the interface 'm'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(SLAVE_DATA_WIDTH - 1):0' is present in all ports of the interface 's'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(MASTER_DATA_WIDTH - 1):0' is present in all ports of the interface 'm'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(SLAVE_DATA_WIDTH - 1):0' is present in all ports of the interface 's'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "s_axis" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"s_valid" "TVALID"} \ -# {"s_ready" "TREADY"} \ -# {"s_data" "TDATA"} \ -# } -# adi_add_bus "m_axis" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"m_valid" "TVALID"} \ -# {"m_ready" "TREADY"} \ -# {"m_data" "TDATA"} \ -# } -# adi_add_bus_clock "clk" "s_axis:m_axis" "resetn" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:18:03 2021... diff --git a/adi_library/util_axis_resize/vivado.jou b/adi_library/util_axis_resize/vivado.jou deleted file mode 100644 index 385a897f..00000000 --- a/adi_library/util_axis_resize/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:17:56 2021 -# Process ID: 7088 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_resize -# Command line: vivado -mode batch -source util_axis_resize_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_resize/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_resize/vivado.jou -#----------------------------------------------------------- -source util_axis_resize_ip.tcl diff --git a/adi_library/util_axis_resize/vivado.log b/adi_library/util_axis_resize/vivado.log deleted file mode 100644 index 79e7a00b..00000000 --- a/adi_library/util_axis_resize/vivado.log +++ /dev/null @@ -1,722 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:17:56 2021 -# Process ID: 7088 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_resize -# Command line: vivado -mode batch -source util_axis_resize_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_resize/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_resize/vivado.jou -#----------------------------------------------------------- -source util_axis_resize_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_axis_resize -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_resize'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_axis_resize [list \ -# "util_axis_resize.v" ] -# adi_ip_properties_lite util_axis_resize -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'count' has a dependency on the module local parameter or undefined parameter 'RATIO'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'count' has a dependency on the module local parameter or undefined parameter 'RATIO'. -WARNING: [IP_Flow 19-5150] The Range '(MASTER_DATA_WIDTH - 1):0' is present in all ports of the interface 'm'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(SLAVE_DATA_WIDTH - 1):0' is present in all ports of the interface 's'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(MASTER_DATA_WIDTH - 1):0' is present in all ports of the interface 'm'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(SLAVE_DATA_WIDTH - 1):0' is present in all ports of the interface 's'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "s_axis" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"s_valid" "TVALID"} \ -# {"s_ready" "TREADY"} \ -# {"s_data" "TDATA"} \ -# } -# adi_add_bus "m_axis" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"m_valid" "TVALID"} \ -# {"m_ready" "TREADY"} \ -# {"m_data" "TDATA"} \ -# } -# adi_add_bus_clock "clk" "s_axis:m_axis" "resetn" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:18:03 2021... diff --git a/adi_library/util_axis_upscale/util_axis_upscale_ip.log b/adi_library/util_axis_upscale/util_axis_upscale_ip.log deleted file mode 100644 index c9b616c4..00000000 --- a/adi_library/util_axis_upscale/util_axis_upscale_ip.log +++ /dev/null @@ -1,718 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_axis_upscale_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_axis_upscale -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_upscale'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_axis_upscale [list \ -# "$ad_hdl_dir/library/common/util_axis_upscale.v"] -# adi_ip_properties_lite util_axis_upscale -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_axis_upscale.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_upscale'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_axis_upscale.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_upscale'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_CHANNELS * UDATA_WIDTH) - 1):0' is present in all ports of the interface 'm_axis'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_CHANNELS * DATA_WIDTH) - 1):0' is present in all ports of the interface 's_axis'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_CHANNELS * UDATA_WIDTH) - 1):0' is present in all ports of the interface 'm_axis'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_CHANNELS * DATA_WIDTH) - 1):0' is present in all ports of the interface 's_axis'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "s_axis" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"s_axis_valid" "TVALID"} \ -# {"s_axis_ready" "TREADY"} \ -# {"s_axis_data" "TDATA"} \ -# } -# adi_add_bus_clock "clk" "s_axis" "resetn" -# adi_add_bus "m_axis" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"m_axis_valid" "TVALID"} \ -# {"m_axis_ready" "TREADY"} \ -# {"m_axis_data" "TDATA"} \ -# } -# ipx::associate_bus_interfaces -busif m_axis -clock s_axis_signal_clock [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:18:10 2021... diff --git a/adi_library/util_axis_upscale/vivado.jou b/adi_library/util_axis_upscale/vivado.jou deleted file mode 100644 index 654871b6..00000000 --- a/adi_library/util_axis_upscale/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:18:04 2021 -# Process ID: 7140 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_upscale -# Command line: vivado -mode batch -source util_axis_upscale_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_upscale/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_upscale/vivado.jou -#----------------------------------------------------------- -source util_axis_upscale_ip.tcl diff --git a/adi_library/util_axis_upscale/vivado.log b/adi_library/util_axis_upscale/vivado.log deleted file mode 100644 index 8428a638..00000000 --- a/adi_library/util_axis_upscale/vivado.log +++ /dev/null @@ -1,723 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:18:04 2021 -# Process ID: 7140 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_upscale -# Command line: vivado -mode batch -source util_axis_upscale_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_upscale/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_upscale/vivado.jou -#----------------------------------------------------------- -source util_axis_upscale_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_axis_upscale -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_upscale'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_axis_upscale [list \ -# "$ad_hdl_dir/library/common/util_axis_upscale.v"] -# adi_ip_properties_lite util_axis_upscale -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_axis_upscale.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_upscale'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_axis_upscale.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_upscale'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_CHANNELS * UDATA_WIDTH) - 1):0' is present in all ports of the interface 'm_axis'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_CHANNELS * DATA_WIDTH) - 1):0' is present in all ports of the interface 's_axis'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_CHANNELS * UDATA_WIDTH) - 1):0' is present in all ports of the interface 'm_axis'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_CHANNELS * DATA_WIDTH) - 1):0' is present in all ports of the interface 's_axis'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "s_axis" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"s_axis_valid" "TVALID"} \ -# {"s_axis_ready" "TREADY"} \ -# {"s_axis_data" "TDATA"} \ -# } -# adi_add_bus_clock "clk" "s_axis" "resetn" -# adi_add_bus "m_axis" "master" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# { -# {"m_axis_valid" "TVALID"} \ -# {"m_axis_ready" "TREADY"} \ -# {"m_axis_data" "TDATA"} \ -# } -# ipx::associate_bus_interfaces -busif m_axis -clock s_axis_signal_clock [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:18:10 2021... diff --git a/adi_library/util_bsplit/util_bsplit_ip.log b/adi_library/util_bsplit/util_bsplit_ip.log deleted file mode 100644 index b731f5d5..00000000 --- a/adi_library/util_bsplit/util_bsplit_ip.log +++ /dev/null @@ -1,742 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_bsplit_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_bsplit -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_bsplit'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_bsplit [list \ -# "util_bsplit.v" ] -# adi_ip_properties_lite util_bsplit -INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 9 for port or parameter 'data_s' -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1}} \ -# [ipx::get_ports *_1* -of_objects [ipx::current_core]] \ -# -# set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2}} \ -# [ipx::get_ports *_2* -of_objects [ipx::current_core]] \ -# -# set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3}} \ -# [ipx::get_ports *_3* -of_objects [ipx::current_core]] \ -# -# set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4}} \ -# [ipx::get_ports *_4* -of_objects [ipx::current_core]] \ -# -# set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5}} \ -# [ipx::get_ports *_5* -of_objects [ipx::current_core]] \ -# -# set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6}} \ -# [ipx::get_ports *_6* -of_objects [ipx::current_core]] \ -# -# set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7}} \ -# [ipx::get_ports *_7* -of_objects [ipx::current_core]] \ -# -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:18:18 2021... diff --git a/adi_library/util_bsplit/vivado.jou b/adi_library/util_bsplit/vivado.jou deleted file mode 100644 index a0bb8b82..00000000 --- a/adi_library/util_bsplit/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:18:11 2021 -# Process ID: 7203 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_bsplit -# Command line: vivado -mode batch -source util_bsplit_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_bsplit/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_bsplit/vivado.jou -#----------------------------------------------------------- -source util_bsplit_ip.tcl diff --git a/adi_library/util_bsplit/vivado.log b/adi_library/util_bsplit/vivado.log deleted file mode 100644 index 98bbc2b6..00000000 --- a/adi_library/util_bsplit/vivado.log +++ /dev/null @@ -1,747 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:18:11 2021 -# Process ID: 7203 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_bsplit -# Command line: vivado -mode batch -source util_bsplit_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_bsplit/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_bsplit/vivado.jou -#----------------------------------------------------------- -source util_bsplit_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_bsplit -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_bsplit'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_bsplit [list \ -# "util_bsplit.v" ] -# adi_ip_properties_lite util_bsplit -INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 9 for port or parameter 'data_s' -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'split_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'split_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'split_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1}} \ -# [ipx::get_ports *_1* -of_objects [ipx::current_core]] \ -# -# set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2}} \ -# [ipx::get_ports *_2* -of_objects [ipx::current_core]] \ -# -# set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3}} \ -# [ipx::get_ports *_3* -of_objects [ipx::current_core]] \ -# -# set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4}} \ -# [ipx::get_ports *_4* -of_objects [ipx::current_core]] \ -# -# set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5}} \ -# [ipx::get_ports *_5* -of_objects [ipx::current_core]] \ -# -# set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6}} \ -# [ipx::get_ports *_6* -of_objects [ipx::current_core]] \ -# -# set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7}} \ -# [ipx::get_ports *_7* -of_objects [ipx::current_core]] \ -# -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:18:18 2021... diff --git a/adi_library/util_cdc/util_cdc_ip.log b/adi_library/util_cdc/util_cdc_ip.log deleted file mode 100644 index 219d01cb..00000000 --- a/adi_library/util_cdc/util_cdc_ip.log +++ /dev/null @@ -1,705 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_cdc_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_cdc -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cdc'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# add_files -fileset [get_filesets sources_1] [list \ -# "sync_gray.v" \ -# "sync_bits.v" \ -# "sync_data.v" \ -# "sync_event.v" \ -# ] -# adi_ip_properties_lite util_cdc -WARNING: [IP_Flow 19-5150] The Range '(NUM_OF_BITS - 1):0' is present in all ports of the interface 'in'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(NUM_OF_BITS - 1):0' is present in all ports of the interface 'out'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'in' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'out' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(NUM_OF_BITS - 1):0' is present in all ports of the interface 'in'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(NUM_OF_BITS - 1):0' is present in all ports of the interface 'out'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'in_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'out_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -WARNING: [IP_Flow 19-1965] Bus Interface 'in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'out_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'in_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'out_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# set_property name "util_cdc" [ipx::current_core] -# set_property display_name "ADI Clock-Domain-Crossing Utils" [ipx::current_core] -# set_property description "ADI Clock-Domain-Crossing Utils" [ipx::current_core] -# set_property hide_in_gui {1} [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:22:24 2021... diff --git a/adi_library/util_cdc/vivado.jou b/adi_library/util_cdc/vivado.jou deleted file mode 100644 index 42a10dce..00000000 --- a/adi_library/util_cdc/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:22:18 2021 -# Process ID: 66451 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cdc -# Command line: vivado -mode batch -source util_cdc_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cdc/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cdc/vivado.jou -#----------------------------------------------------------- -source util_cdc_ip.tcl diff --git a/adi_library/util_cdc/vivado.log b/adi_library/util_cdc/vivado.log deleted file mode 100644 index f88cf320..00000000 --- a/adi_library/util_cdc/vivado.log +++ /dev/null @@ -1,710 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:22:18 2021 -# Process ID: 66451 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cdc -# Command line: vivado -mode batch -source util_cdc_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cdc/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cdc/vivado.jou -#----------------------------------------------------------- -source util_cdc_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_cdc -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cdc'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# add_files -fileset [get_filesets sources_1] [list \ -# "sync_gray.v" \ -# "sync_bits.v" \ -# "sync_data.v" \ -# "sync_event.v" \ -# ] -# adi_ip_properties_lite util_cdc -WARNING: [IP_Flow 19-5150] The Range '(NUM_OF_BITS - 1):0' is present in all ports of the interface 'in'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(NUM_OF_BITS - 1):0' is present in all ports of the interface 'out'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'in' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'out' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(NUM_OF_BITS - 1):0' is present in all ports of the interface 'in'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(NUM_OF_BITS - 1):0' is present in all ports of the interface 'out'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'in_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'out_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -WARNING: [IP_Flow 19-1965] Bus Interface 'in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'out_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'in_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'out_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# set_property name "util_cdc" [ipx::current_core] -# set_property display_name "ADI Clock-Domain-Crossing Utils" [ipx::current_core] -# set_property description "ADI Clock-Domain-Crossing Utils" [ipx::current_core] -# set_property hide_in_gui {1} [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:22:24 2021... diff --git a/adi_library/util_cic/util_cic_ip.log b/adi_library/util_cic/util_cic_ip.log deleted file mode 100644 index 0c5010d2..00000000 --- a/adi_library/util_cic/util_cic_ip.log +++ /dev/null @@ -1,689 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_cic_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_cic -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# add_files -fileset [get_filesets sources_1] [list \ -# "cic_int.v" \ -# "cic_comb.v" \ -# ] -# adi_ip_properties_lite util_cic -WARNING: [IP_Flow 19-5150] The Range '(NUM_STAGES - 1):0' is present in all ports of the interface 'interface_spi_engine_offload_ctrl'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# set_property name "util_cic" [ipx::current_core] -# set_property display_name "CIC building blocks" [ipx::current_core] -# set_property description "CIC building blocks" [ipx::current_core] -# set_property hide_in_gui {1} [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:12:42 2021... diff --git a/adi_library/util_cic/vivado.jou b/adi_library/util_cic/vivado.jou deleted file mode 100644 index 008a71ed..00000000 --- a/adi_library/util_cic/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:12:36 2021 -# Process ID: 4912 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic -# Command line: vivado -mode batch -source util_cic_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic/vivado.jou -#----------------------------------------------------------- -source util_cic_ip.tcl diff --git a/adi_library/util_cic/vivado.log b/adi_library/util_cic/vivado.log deleted file mode 100644 index de7118f1..00000000 --- a/adi_library/util_cic/vivado.log +++ /dev/null @@ -1,694 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:12:36 2021 -# Process ID: 4912 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic -# Command line: vivado -mode batch -source util_cic_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic/vivado.jou -#----------------------------------------------------------- -source util_cic_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_cic -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# add_files -fileset [get_filesets sources_1] [list \ -# "cic_int.v" \ -# "cic_comb.v" \ -# ] -# adi_ip_properties_lite util_cic -WARNING: [IP_Flow 19-5150] The Range '(NUM_STAGES - 1):0' is present in all ports of the interface 'interface_spi_engine_offload_ctrl'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# set_property name "util_cic" [ipx::current_core] -# set_property display_name "CIC building blocks" [ipx::current_core] -# set_property description "CIC building blocks" [ipx::current_core] -# set_property hide_in_gui {1} [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:12:42 2021... diff --git a/adi_library/util_dacfifo/util_dacfifo_ip.log b/adi_library/util_dacfifo/util_dacfifo_ip.log deleted file mode 100644 index 6eb2cf33..00000000 --- a/adi_library/util_dacfifo/util_dacfifo_ip.log +++ /dev/null @@ -1,728 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_dacfifo_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_dacfifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_dacfifo [list \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "$ad_hdl_dir/library/common/ad_mem_asym.v" \ -# "$ad_hdl_dir/library/common/ad_b2g.v" \ -# "$ad_hdl_dir/library/common/ad_g2b.v" \ -# "util_dacfifo.v" \ -# "util_dacfifo_bypass.v" \ -# "util_dacfifo_ooc.ttcl" \ -# "util_dacfifo_constr.xdc"] -# adi_ip_properties_lite util_dacfifo -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo/util_dacfifo_ooc.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_b2g.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_g2b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_b2g.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_g2b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'dma'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_rst'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_xfer_req' and definition port 'XFER_REQ'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_ttcl util_dacfifo "util_dacfifo_ooc.ttcl" -# ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dma_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_rst'. -# ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:18:29 2021... diff --git a/adi_library/util_dacfifo/vivado.jou b/adi_library/util_dacfifo/vivado.jou deleted file mode 100644 index 96444da9..00000000 --- a/adi_library/util_dacfifo/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:18:19 2021 -# Process ID: 7265 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo -# Command line: vivado -mode batch -source util_dacfifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo/vivado.jou -#----------------------------------------------------------- -source util_dacfifo_ip.tcl diff --git a/adi_library/util_dacfifo/vivado.log b/adi_library/util_dacfifo/vivado.log deleted file mode 100644 index 76088ae3..00000000 --- a/adi_library/util_dacfifo/vivado.log +++ /dev/null @@ -1,733 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:18:19 2021 -# Process ID: 7265 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo -# Command line: vivado -mode batch -source util_dacfifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo/vivado.jou -#----------------------------------------------------------- -source util_dacfifo_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_dacfifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_dacfifo [list \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "$ad_hdl_dir/library/common/ad_mem_asym.v" \ -# "$ad_hdl_dir/library/common/ad_b2g.v" \ -# "$ad_hdl_dir/library/common/ad_g2b.v" \ -# "util_dacfifo.v" \ -# "util_dacfifo_bypass.v" \ -# "util_dacfifo_ooc.ttcl" \ -# "util_dacfifo_constr.xdc"] -# adi_ip_properties_lite util_dacfifo -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo/util_dacfifo_ooc.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_b2g.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_g2b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_b2g.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_g2b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'dma'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_rst'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_xfer_req' and definition port 'XFER_REQ'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_ttcl util_dacfifo "util_dacfifo_ooc.ttcl" -# ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dma_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_rst'. -# ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:18:29 2021... diff --git a/adi_library/util_dec256sinc24b/util_dec256sinc24b_ip.log b/adi_library/util_dec256sinc24b/util_dec256sinc24b_ip.log deleted file mode 100644 index cc63aead..00000000 --- a/adi_library/util_dec256sinc24b/util_dec256sinc24b_ip.log +++ /dev/null @@ -1,698 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_dec256sinc24b_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_dec256sinc24b -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dec256sinc24b'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_dec256sinc24b [list \ -# "$ad_hdl_dir/library/common/util_dec256sinc24b.v"] -# adi_ip_properties_lite util_dec256sinc24b -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_dec256sinc24b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dec256sinc24b'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_dec256sinc24b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dec256sinc24b'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dec'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data_en' and definition port 'EN'. -WARNING: [IP_Flow 19-1965] Bus Interface 'data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:18:37 2021... diff --git a/adi_library/util_dec256sinc24b/vivado.jou b/adi_library/util_dec256sinc24b/vivado.jou deleted file mode 100644 index 5e585b06..00000000 --- a/adi_library/util_dec256sinc24b/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:18:30 2021 -# Process ID: 7331 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dec256sinc24b -# Command line: vivado -mode batch -source util_dec256sinc24b_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dec256sinc24b/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dec256sinc24b/vivado.jou -#----------------------------------------------------------- -source util_dec256sinc24b_ip.tcl diff --git a/adi_library/util_dec256sinc24b/vivado.log b/adi_library/util_dec256sinc24b/vivado.log deleted file mode 100644 index b40f0642..00000000 --- a/adi_library/util_dec256sinc24b/vivado.log +++ /dev/null @@ -1,703 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:18:30 2021 -# Process ID: 7331 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dec256sinc24b -# Command line: vivado -mode batch -source util_dec256sinc24b_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dec256sinc24b/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dec256sinc24b/vivado.jou -#----------------------------------------------------------- -source util_dec256sinc24b_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_dec256sinc24b -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dec256sinc24b'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_dec256sinc24b [list \ -# "$ad_hdl_dir/library/common/util_dec256sinc24b.v"] -# adi_ip_properties_lite util_dec256sinc24b -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_dec256sinc24b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dec256sinc24b'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_dec256sinc24b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dec256sinc24b'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dec'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data_en' and definition port 'EN'. -WARNING: [IP_Flow 19-1965] Bus Interface 'data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:18:37 2021... diff --git a/adi_library/util_delay/util_delay_ip.log b/adi_library/util_delay/util_delay_ip.log deleted file mode 100644 index 063e4550..00000000 --- a/adi_library/util_delay/util_delay_ip.log +++ /dev/null @@ -1,693 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_delay_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_delay -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_delay'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_delay [list \ -# "$ad_hdl_dir/library/common/util_delay.v"] -# adi_ip_properties_lite util_delay -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_delay.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_delay'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_delay.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_delay'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -# set_property value_validation_range_minimum 1 [ipx::get_user_parameters DELAY_CYCLES -of_objects [ipx::current_core]] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:18:44 2021... diff --git a/adi_library/util_delay/vivado.jou b/adi_library/util_delay/vivado.jou deleted file mode 100644 index ac85b7d1..00000000 --- a/adi_library/util_delay/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:18:37 2021 -# Process ID: 7383 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_delay -# Command line: vivado -mode batch -source util_delay_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_delay/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_delay/vivado.jou -#----------------------------------------------------------- -source util_delay_ip.tcl diff --git a/adi_library/util_delay/vivado.log b/adi_library/util_delay/vivado.log deleted file mode 100644 index d365b291..00000000 --- a/adi_library/util_delay/vivado.log +++ /dev/null @@ -1,698 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:18:37 2021 -# Process ID: 7383 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_delay -# Command line: vivado -mode batch -source util_delay_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_delay/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_delay/vivado.jou -#----------------------------------------------------------- -source util_delay_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_delay -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_delay'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_delay [list \ -# "$ad_hdl_dir/library/common/util_delay.v"] -# adi_ip_properties_lite util_delay -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_delay.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_delay'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_delay.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_delay'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -# set_property value_validation_range_minimum 1 [ipx::get_user_parameters DELAY_CYCLES -of_objects [ipx::current_core]] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:18:44 2021... diff --git a/adi_library/util_extract/util_extract_ip.log b/adi_library/util_extract/util_extract_ip.log deleted file mode 100644 index 65df935b..00000000 --- a/adi_library/util_extract/util_extract_ip.log +++ /dev/null @@ -1,692 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_extract_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_extract -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_extract'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_extract [list \ -# "util_extract.v" ] -# adi_ip_properties_lite util_extract -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-818] Not transferring value dependency attribute "(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) * 16)" into user parameter "DATA_WIDTH". -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:18:52 2021... diff --git a/adi_library/util_extract/vivado.jou b/adi_library/util_extract/vivado.jou deleted file mode 100644 index 9d921bce..00000000 --- a/adi_library/util_extract/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:18:45 2021 -# Process ID: 7436 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_extract -# Command line: vivado -mode batch -source util_extract_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_extract/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_extract/vivado.jou -#----------------------------------------------------------- -source util_extract_ip.tcl diff --git a/adi_library/util_extract/vivado.log b/adi_library/util_extract/vivado.log deleted file mode 100644 index 487dbd38..00000000 --- a/adi_library/util_extract/vivado.log +++ /dev/null @@ -1,697 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:18:45 2021 -# Process ID: 7436 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_extract -# Command line: vivado -mode batch -source util_extract_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_extract/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_extract/vivado.jou -#----------------------------------------------------------- -source util_extract_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_extract -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_extract'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_extract [list \ -# "util_extract.v" ] -# adi_ip_properties_lite util_extract -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-818] Not transferring value dependency attribute "(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) * 16)" into user parameter "DATA_WIDTH". -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:18:52 2021... diff --git a/adi_library/util_fir_dec/util_fir_dec_ip.log b/adi_library/util_fir_dec/util_fir_dec_ip.log deleted file mode 100644 index 2caec9ae..00000000 --- a/adi_library/util_fir_dec/util_fir_dec_ip.log +++ /dev/null @@ -1,897 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_fir_dec_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_fir_dec -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_dec'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# set fir_decim [create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_decim] -# set_property -dict [ list \ -# CONFIG.Clock_Frequency {61.44} \ -# CONFIG.CoefficientSource {COE_File} \ -# CONFIG.Coefficient_File {../../../../coefile_dec.coe} \ -# CONFIG.Coefficient_Fractional_Bits {0} \ -# CONFIG.Data_Fractional_Bits {15} \ -# CONFIG.Coefficient_Sets {1} \ -# CONFIG.Coefficient_Sign {Signed} \ -# CONFIG.Coefficient_Structure {Inferred} \ -# CONFIG.Coefficient_Width {16} \ -# CONFIG.ColumnConfig {5} \ -# CONFIG.Decimation_Rate {8} \ -# CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ -# CONFIG.Filter_Type {Decimation} \ -# CONFIG.Interpolation_Rate {1} \ -# CONFIG.Number_Channels {1} \ -# CONFIG.Number_Paths {2} \ -# CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ -# CONFIG.Output_Width {16} \ -# CONFIG.Quantization {Integer_Coefficients} \ -# CONFIG.RateSpecification {Frequency_Specification} \ -# CONFIG.Sample_Frequency {61.44} \ -# CONFIG.Zero_Pack_Factor {1} \ -# ] [get_ips fir_decim] -WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'ColumnConfig' from '9' to '5' has been ignored for IP 'fir_decim' -# generate_target {all} [get_files util_fir_dec.srcs/sources_1/ip/fir_decim/fir_decim.xci] -INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fir_decim'... -INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fir_decim'... -INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fir_decim'... -INFO: [IP_Flow 19-1686] Generating 'C Simulation' target for IP 'fir_decim'... -INFO: [IP_Flow 19-1686] Generating 'Test Bench' target for IP 'fir_decim'... -INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'fir_decim'... -INFO: [xilinx.com:ip:fir_compiler:7.2-1] fir_decim: Coefficient Reload not selected, no files generated -INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'fir_decim'... -# adi_ip_files util_fir_dec [list \ -# "util_fir_dec.v" ] -# adi_ip_properties_lite util_fir_dec -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tvalid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tvalid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_data' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_data' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis_data'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tvalid' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tvalid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_data_tready' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tvalid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:00 2021... diff --git a/adi_library/util_fir_dec/vivado.jou b/adi_library/util_fir_dec/vivado.jou deleted file mode 100644 index a87aa4aa..00000000 --- a/adi_library/util_fir_dec/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:18:52 2021 -# Process ID: 7489 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_dec -# Command line: vivado -mode batch -source util_fir_dec_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_dec/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_dec/vivado.jou -#----------------------------------------------------------- -source util_fir_dec_ip.tcl diff --git a/adi_library/util_fir_dec/vivado.log b/adi_library/util_fir_dec/vivado.log deleted file mode 100644 index 5744abae..00000000 --- a/adi_library/util_fir_dec/vivado.log +++ /dev/null @@ -1,902 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:18:52 2021 -# Process ID: 7489 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_dec -# Command line: vivado -mode batch -source util_fir_dec_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_dec/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_dec/vivado.jou -#----------------------------------------------------------- -source util_fir_dec_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_fir_dec -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_dec'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# set fir_decim [create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_decim] -# set_property -dict [ list \ -# CONFIG.Clock_Frequency {61.44} \ -# CONFIG.CoefficientSource {COE_File} \ -# CONFIG.Coefficient_File {../../../../coefile_dec.coe} \ -# CONFIG.Coefficient_Fractional_Bits {0} \ -# CONFIG.Data_Fractional_Bits {15} \ -# CONFIG.Coefficient_Sets {1} \ -# CONFIG.Coefficient_Sign {Signed} \ -# CONFIG.Coefficient_Structure {Inferred} \ -# CONFIG.Coefficient_Width {16} \ -# CONFIG.ColumnConfig {5} \ -# CONFIG.Decimation_Rate {8} \ -# CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ -# CONFIG.Filter_Type {Decimation} \ -# CONFIG.Interpolation_Rate {1} \ -# CONFIG.Number_Channels {1} \ -# CONFIG.Number_Paths {2} \ -# CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ -# CONFIG.Output_Width {16} \ -# CONFIG.Quantization {Integer_Coefficients} \ -# CONFIG.RateSpecification {Frequency_Specification} \ -# CONFIG.Sample_Frequency {61.44} \ -# CONFIG.Zero_Pack_Factor {1} \ -# ] [get_ips fir_decim] -WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'ColumnConfig' from '9' to '5' has been ignored for IP 'fir_decim' -# generate_target {all} [get_files util_fir_dec.srcs/sources_1/ip/fir_decim/fir_decim.xci] -INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fir_decim'... -INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fir_decim'... -INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fir_decim'... -INFO: [IP_Flow 19-1686] Generating 'C Simulation' target for IP 'fir_decim'... -INFO: [IP_Flow 19-1686] Generating 'Test Bench' target for IP 'fir_decim'... -INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'fir_decim'... -INFO: [xilinx.com:ip:fir_compiler:7.2-1] fir_decim: Coefficient Reload not selected, no files generated -INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'fir_decim'... -# adi_ip_files util_fir_dec [list \ -# "util_fir_dec.v" ] -# adi_ip_properties_lite util_fir_dec -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tdata_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tvalid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tvalid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_data' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_data' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis_data'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tdata' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tdata_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tvalid' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tvalid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_data_tready' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tvalid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:00 2021... diff --git a/adi_library/util_fir_int/util_fir_int_ip.log b/adi_library/util_fir_int/util_fir_int_ip.log deleted file mode 100644 index 18574cc6..00000000 --- a/adi_library/util_fir_int/util_fir_int_ip.log +++ /dev/null @@ -1,866 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_fir_int_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_fir_int -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_int'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# set fir_interp [create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_interp] -# set_property -dict [ list \ -# CONFIG.Clock_Frequency {61.44} \ -# CONFIG.CoefficientSource {COE_File} \ -# CONFIG.Coefficient_File {../../../../coefile_int.coe} \ -# CONFIG.Coefficient_Fractional_Bits {0} \ -# CONFIG.Data_Fractional_Bits {15} \ -# CONFIG.Coefficient_Sets {1} \ -# CONFIG.Coefficient_Sign {Signed} \ -# CONFIG.S_DATA_Has_FIFO {true} \ -# CONFIG.Coefficient_Structure {Inferred} \ -# CONFIG.Coefficient_Width {16} \ -# CONFIG.ColumnConfig {5} \ -# CONFIG.Decimation_Rate {1} \ -# CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ -# CONFIG.Filter_Type {Interpolation} \ -# CONFIG.Interpolation_Rate {8} \ -# CONFIG.M_DATA_Has_TREADY {false} \ -# CONFIG.Number_Channels {1} \ -# CONFIG.Number_Paths {2} \ -# CONFIG.Output_Rounding_Mode {Truncate_LSBs} \ -# CONFIG.Output_Width {16} \ -# CONFIG.Quantization {Integer_Coefficients} \ -# CONFIG.RateSpecification {Frequency_Specification} \ -# CONFIG.Sample_Frequency {7.68} \ -# CONFIG.Zero_Pack_Factor {1} \ -# ] [get_ips fir_interp] -WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'ColumnConfig' from '9' to '5' has been ignored for IP 'fir_interp' -# generate_target {all} [get_files util_fir_int.srcs/sources_1/ip/fir_interp/fir_interp.xci] -INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fir_interp'... -INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fir_interp'... -INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fir_interp'... -INFO: [IP_Flow 19-1686] Generating 'C Simulation' target for IP 'fir_interp'... -INFO: [IP_Flow 19-1686] Generating 'Test Bench' target for IP 'fir_interp'... -INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'fir_interp'... -INFO: [xilinx.com:ip:fir_compiler:7.2-1] fir_interp: Coefficient Reload not selected, no files generated -INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'fir_interp'... -# adi_ip_files util_fir_int [list \ -# "util_fir_int.v" ] -# adi_ip_properties_lite util_fir_int -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tvalid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tvalid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_data' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis_data'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tvalid' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tvalid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_data_tready' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tvalid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:08 2021... diff --git a/adi_library/util_fir_int/vivado.jou b/adi_library/util_fir_int/vivado.jou deleted file mode 100644 index c6db55f0..00000000 --- a/adi_library/util_fir_int/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:01 2021 -# Process ID: 7545 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_int -# Command line: vivado -mode batch -source util_fir_int_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_int/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_int/vivado.jou -#----------------------------------------------------------- -source util_fir_int_ip.tcl diff --git a/adi_library/util_fir_int/vivado.log b/adi_library/util_fir_int/vivado.log deleted file mode 100644 index 34ed8fca..00000000 --- a/adi_library/util_fir_int/vivado.log +++ /dev/null @@ -1,871 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:01 2021 -# Process ID: 7545 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_int -# Command line: vivado -mode batch -source util_fir_int_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_int/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_int/vivado.jou -#----------------------------------------------------------- -source util_fir_int_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_fir_int -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_fir_int'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# set fir_interp [create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_interp] -# set_property -dict [ list \ -# CONFIG.Clock_Frequency {61.44} \ -# CONFIG.CoefficientSource {COE_File} \ -# CONFIG.Coefficient_File {../../../../coefile_int.coe} \ -# CONFIG.Coefficient_Fractional_Bits {0} \ -# CONFIG.Data_Fractional_Bits {15} \ -# CONFIG.Coefficient_Sets {1} \ -# CONFIG.Coefficient_Sign {Signed} \ -# CONFIG.S_DATA_Has_FIFO {true} \ -# CONFIG.Coefficient_Structure {Inferred} \ -# CONFIG.Coefficient_Width {16} \ -# CONFIG.ColumnConfig {5} \ -# CONFIG.Decimation_Rate {1} \ -# CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ -# CONFIG.Filter_Type {Interpolation} \ -# CONFIG.Interpolation_Rate {8} \ -# CONFIG.M_DATA_Has_TREADY {false} \ -# CONFIG.Number_Channels {1} \ -# CONFIG.Number_Paths {2} \ -# CONFIG.Output_Rounding_Mode {Truncate_LSBs} \ -# CONFIG.Output_Width {16} \ -# CONFIG.Quantization {Integer_Coefficients} \ -# CONFIG.RateSpecification {Frequency_Specification} \ -# CONFIG.Sample_Frequency {7.68} \ -# CONFIG.Zero_Pack_Factor {1} \ -# ] [get_ips fir_interp] -WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'ColumnConfig' from '9' to '5' has been ignored for IP 'fir_interp' -# generate_target {all} [get_files util_fir_int.srcs/sources_1/ip/fir_interp/fir_interp.xci] -INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fir_interp'... -INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fir_interp'... -INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fir_interp'... -INFO: [IP_Flow 19-1686] Generating 'C Simulation' target for IP 'fir_interp'... -INFO: [IP_Flow 19-1686] Generating 'Test Bench' target for IP 'fir_interp'... -INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'fir_interp'... -INFO: [xilinx.com:ip:fir_compiler:7.2-1] fir_interp: Coefficient Reload not selected, no files generated -INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'fir_interp'... -# adi_ip_files util_fir_int [list \ -# "util_fir_int.v" ] -# adi_ip_properties_lite util_fir_int -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_tvalid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tdata_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_tvalid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axis_tdata'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_data' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis_data'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data_tvalid' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis_tvalid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tdata_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 's_axis_data_tready' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis_tvalid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:08 2021... diff --git a/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.log b/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.log deleted file mode 100644 index 7682e34c..00000000 --- a/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.log +++ /dev/null @@ -1,738 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_gmii_to_rgmii_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_gmii_to_rgmii -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_gmii_to_rgmii'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_gmii_to_rgmii [list \ -# "mdc_mdio.v" \ -# "util_gmii_to_rgmii_constr.xdc" \ -# "util_gmii_to_rgmii.v" ] -# adi_ip_properties_lite util_gmii_to_rgmii -INFO: [IP_Flow 19-4821] For module 'util_gmii_to_rgmii', parameter 'IODELAY_CTRL' is inferred to be bitString format. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'gmii_tx' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '3:0' is present in all ports of the interface 'rgmii'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rgmii_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rgmii_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rgmii_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rgmii_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'gmii_rx_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'gmii_tx_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'idelayctrl_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -WARNING: [IP_Flow 19-1965] Bus Interface 'gmii_tx': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'gmii_rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'gmii_rx_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'gmii_tx_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'gmii_tx_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'idelayctrl_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::infer_bus_interface {gmii_tx_clk gmii_txd gmii_tx_en gmii_tx_er gmii_crs gmii_col gmii_rx_clk gmii_rxd gmii_rx_dv gmii_rx_er} xilinx.com:interface:gmii_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'gmii' of definition 'xilinx.com:interface:gmii:1.0' (from TCL Argument). -# ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core] -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rgmii' of definition 'xilinx.com:interface:rgmii:1.0' (from TCL Argument). -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.IODELAY_CTRL')) = 1} \ -# [ipx::get_ports idelayctrl_clk -of_objects [ipx::current_core]] -# ipx::infer_bus_interface clk_20m xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_20m' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface clk_25m xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_25m' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface clk_125m xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_125m' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface idelayctrl_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'idelayctrl_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:16 2021... diff --git a/adi_library/util_gmii_to_rgmii/vivado.jou b/adi_library/util_gmii_to_rgmii/vivado.jou deleted file mode 100644 index 9d5ced39..00000000 --- a/adi_library/util_gmii_to_rgmii/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:09 2021 -# Process ID: 7604 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_gmii_to_rgmii -# Command line: vivado -mode batch -source util_gmii_to_rgmii_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_gmii_to_rgmii/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_gmii_to_rgmii/vivado.jou -#----------------------------------------------------------- -source util_gmii_to_rgmii_ip.tcl diff --git a/adi_library/util_gmii_to_rgmii/vivado.log b/adi_library/util_gmii_to_rgmii/vivado.log deleted file mode 100644 index afde8766..00000000 --- a/adi_library/util_gmii_to_rgmii/vivado.log +++ /dev/null @@ -1,743 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:09 2021 -# Process ID: 7604 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_gmii_to_rgmii -# Command line: vivado -mode batch -source util_gmii_to_rgmii_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_gmii_to_rgmii/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_gmii_to_rgmii/vivado.jou -#----------------------------------------------------------- -source util_gmii_to_rgmii_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_gmii_to_rgmii -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_gmii_to_rgmii'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_gmii_to_rgmii [list \ -# "mdc_mdio.v" \ -# "util_gmii_to_rgmii_constr.xdc" \ -# "util_gmii_to_rgmii.v" ] -# adi_ip_properties_lite util_gmii_to_rgmii -INFO: [IP_Flow 19-4821] For module 'util_gmii_to_rgmii', parameter 'IODELAY_CTRL' is inferred to be bitString format. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'gmii_tx' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5151] The Range '3:0' is present in all ports of the interface 'rgmii'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rgmii_0' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rgmii_1' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rgmii_2' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port data on bus interface abstraction jesd204_tx_ilas_config_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rgmii_3' of definition 'analog.com:interface:jesd204_tx_ilas_config:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'gmii_rx_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'gmii_tx_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'idelayctrl_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -WARNING: [IP_Flow 19-1965] Bus Interface 'gmii_tx': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'rgmii_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'gmii_rx_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'gmii_rx_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'gmii_tx_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-4751] Bus Interface 'gmii_tx_clk': FREQ_HZ bus parameter is missing for output clock interface. -WARNING: [IP_Flow 19-3153] Bus Interface 'idelayctrl_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::infer_bus_interface {gmii_tx_clk gmii_txd gmii_tx_en gmii_tx_er gmii_crs gmii_col gmii_rx_clk gmii_rxd gmii_rx_dv gmii_rx_er} xilinx.com:interface:gmii_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'gmii' of definition 'xilinx.com:interface:gmii:1.0' (from TCL Argument). -# ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core] -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rgmii' of definition 'xilinx.com:interface:rgmii:1.0' (from TCL Argument). -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.IODELAY_CTRL')) = 1} \ -# [ipx::get_ports idelayctrl_clk -of_objects [ipx::current_core]] -# ipx::infer_bus_interface clk_20m xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_20m' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface clk_25m xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_25m' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface clk_125m xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_125m' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface idelayctrl_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'idelayctrl_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:16 2021... diff --git a/adi_library/util_i2c_mixer/util_i2c_mixer_ip.log b/adi_library/util_i2c_mixer/util_i2c_mixer_ip.log deleted file mode 100644 index 1a10d507..00000000 --- a/adi_library/util_i2c_mixer/util_i2c_mixer_ip.log +++ /dev/null @@ -1,691 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_i2c_mixer_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_i2c_mixer -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_i2c_mixer'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_i2c_mixer [list \ -# "util_i2c_mixer.vhd" ] -# adi_ip_properties_lite util_i2c_mixer -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "upstream" "slave" \ -# "xilinx.com:interface:iic_rtl:1.0" \ -# "xilinx.com:interface:iic:1.0" \ -# [list \ -# {"upstream_scl_I" "SCL_O"} \ -# {"upstream_scl_O" "SCL_I"} \ -# {"upstream_scl_T" "SCL_T"} \ -# {"upstream_sda_I" "SDA_O"} \ -# {"upstream_sda_O" "SDA_I"} \ -# {"upstream_sda_T" "SDA_T"} \ -# ] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:24 2021... diff --git a/adi_library/util_i2c_mixer/vivado.jou b/adi_library/util_i2c_mixer/vivado.jou deleted file mode 100644 index 78f79b6b..00000000 --- a/adi_library/util_i2c_mixer/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:17 2021 -# Process ID: 7659 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_i2c_mixer -# Command line: vivado -mode batch -source util_i2c_mixer_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_i2c_mixer/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_i2c_mixer/vivado.jou -#----------------------------------------------------------- -source util_i2c_mixer_ip.tcl diff --git a/adi_library/util_i2c_mixer/vivado.log b/adi_library/util_i2c_mixer/vivado.log deleted file mode 100644 index add3a18c..00000000 --- a/adi_library/util_i2c_mixer/vivado.log +++ /dev/null @@ -1,696 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:17 2021 -# Process ID: 7659 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_i2c_mixer -# Command line: vivado -mode batch -source util_i2c_mixer_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_i2c_mixer/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_i2c_mixer/vivado.jou -#----------------------------------------------------------- -source util_i2c_mixer_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_i2c_mixer -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_i2c_mixer'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_i2c_mixer [list \ -# "util_i2c_mixer.vhd" ] -# adi_ip_properties_lite util_i2c_mixer -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "upstream" "slave" \ -# "xilinx.com:interface:iic_rtl:1.0" \ -# "xilinx.com:interface:iic:1.0" \ -# [list \ -# {"upstream_scl_I" "SCL_O"} \ -# {"upstream_scl_O" "SCL_I"} \ -# {"upstream_scl_T" "SCL_T"} \ -# {"upstream_sda_I" "SDA_O"} \ -# {"upstream_sda_O" "SDA_I"} \ -# {"upstream_sda_T" "SDA_T"} \ -# ] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:24 2021... diff --git a/adi_library/util_mfifo/util_mfifo_ip.log b/adi_library/util_mfifo/util_mfifo_ip.log deleted file mode 100644 index 5bf7a027..00000000 --- a/adi_library/util_mfifo/util_mfifo_ip.log +++ /dev/null @@ -1,1356 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_mfifo_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_mfifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_mfifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_mfifo [list \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "util_mfifo.v" ] -# adi_ip_properties_lite util_mfifo -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_mfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_mfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 'din_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'din_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'dout_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dout_rst'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'din_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dout_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# set_property driver_value 0 [ipx::get_ports *din_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \ -# [ipx::get_ports *_1* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \ -# [ipx::get_ports *_2* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \ -# [ipx::get_ports *_3* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \ -# [ipx::get_ports *_4* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \ -# [ipx::get_ports *_5* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \ -# [ipx::get_ports *_6* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \ -# [ipx::get_ports *_7* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface din_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface din_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'din_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'din_rst'. -# ipx::infer_bus_interface dout_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface dout_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'dout_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dout_rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:32 2021... diff --git a/adi_library/util_mfifo/vivado.jou b/adi_library/util_mfifo/vivado.jou deleted file mode 100644 index 94a9a618..00000000 --- a/adi_library/util_mfifo/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:24 2021 -# Process ID: 7711 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_mfifo -# Command line: vivado -mode batch -source util_mfifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_mfifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_mfifo/vivado.jou -#----------------------------------------------------------- -source util_mfifo_ip.tcl diff --git a/adi_library/util_mfifo/vivado.log b/adi_library/util_mfifo/vivado.log deleted file mode 100644 index a5edcabc..00000000 --- a/adi_library/util_mfifo/vivado.log +++ /dev/null @@ -1,1361 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:24 2021 -# Process ID: 7711 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_mfifo -# Command line: vivado -mode batch -source util_mfifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_mfifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_mfifo/vivado.jou -#----------------------------------------------------------- -source util_mfifo_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_mfifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_mfifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_mfifo [list \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "util_mfifo.v" ] -# adi_ip_properties_lite util_mfifo -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_mfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_mfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dout_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-4728] Bus Interface 'din_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'din_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'dout_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dout_rst'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'din_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dout_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# set_property driver_value 0 [ipx::get_ports *din_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \ -# [ipx::get_ports *_1* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \ -# [ipx::get_ports *_2* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \ -# [ipx::get_ports *_3* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \ -# [ipx::get_ports *_4* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \ -# [ipx::get_ports *_5* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \ -# [ipx::get_ports *_6* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \ -# [ipx::get_ports *_7* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface din_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface din_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'din_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'din_rst'. -# ipx::infer_bus_interface dout_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface dout_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'dout_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dout_rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:32 2021... diff --git a/adi_library/util_pack/util_cpack2/util_cpack2_ip.log b/adi_library/util_pack/util_cpack2/util_cpack2_ip.log deleted file mode 100644 index b8e6aa31..00000000 --- a/adi_library/util_pack/util_cpack2/util_cpack2_ip.log +++ /dev/null @@ -1,1093 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_cpack2_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_cpack2 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_cpack2 [list \ -# "../../common/ad_perfect_shuffle.v" \ -# "../util_pack_common/pack_ctrl.v" \ -# "../util_pack_common/pack_interconnect.v" \ -# "../util_pack_common/pack_network.v" \ -# "../util_pack_common/pack_shell.v" \ -# "util_cpack2_impl.v" \ -# "util_cpack2.v" ] -# adi_ip_properties_lite util_cpack2 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_ctrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_interconnect.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_network.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_shell.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_ctrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_interconnect.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_network.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_shell.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'enable' has a dependency on the module local parameter or undefined parameter 'REAL_NUM_OF_CHANNELS'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'fifo_wr_data' has a dependency on the module local parameter or undefined parameter 'CHANNEL_DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'fifo_wr_data' has a dependency on the module local parameter or undefined parameter 'REAL_NUM_OF_CHANNELS'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'fifo_wr_data_s' has a dependency on the module local parameter or undefined parameter 'CHANNEL_DATA_WIDTH'. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_10'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_11'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_12'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_13'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_14'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_15'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_16'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_17'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_18'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_19'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_20'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_21'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_22'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_23'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_24'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_25'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_26'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_27'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_28'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_29'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_30'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_31'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_32'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_33'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_34'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_35'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_36'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_37'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_38'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_39'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_40'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_41'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_42'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_43'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_44'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_45'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_46'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_47'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_48'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_49'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_50'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_51'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_52'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_53'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_54'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_55'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_56'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_57'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_58'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_59'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_60'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_61'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_62'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_63'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_8'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_9'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'packed_fifo_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_10'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_11'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_12'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_13'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_14'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_15'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_16'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_17'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_18'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_19'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_20'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_21'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_22'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_23'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_24'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_25'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_26'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_27'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_28'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_29'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_30'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_31'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_32'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_33'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_34'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_35'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_36'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_37'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_38'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_39'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_40'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [Common 17-14] Message 'IP_Flow 19-5150' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "packed_fifo_wr" "master" \ -# "analog.com:interface:fifo_wr_rtl:1.0" \ -# "analog.com:interface:fifo_wr:1.0" \ -# { \ -# {"packed_fifo_wr_en" "EN"} \ -# {"packed_fifo_wr_data" "DATA"} \ -# {"packed_fifo_wr_overflow" "OVERFLOW"} \ -# {"packed_fifo_wr_sync" "SYNC"} \ -# } -# adi_add_bus_clock "clk" "packed_fifo_wr" "reset" -# set cc [ipx::current_core] -# for {set i 1} {$i < 64} {incr i} { -# set_property enablement_dependency "spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i" \ -# [ipx::get_ports *_$i -of_objects $cc] -# } -# foreach {k v} { \ -# "NUM_OF_CHANNELS" "Number of Channels" \ -# "SAMPLES_PER_CHANNEL" "Samples per Channel" \ -# "SAMPLE_DATA_WIDTH" "Sample Width" \ -# } { \ -# set p [ipgui::get_guiparamspec -name $k -component $cc] -# # ipgui::move_param -component $cc -order $i $p -parent $ -# set_property -dict [list \ -# DISPLAY_NAME $v \ -# ] $p -# incr i -# } -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:23:54 2021... diff --git a/adi_library/util_pack/util_cpack2/vivado.jou b/adi_library/util_pack/util_cpack2/vivado.jou deleted file mode 100644 index d16485e0..00000000 --- a/adi_library/util_pack/util_cpack2/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:23:44 2021 -# Process ID: 66943 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2 -# Command line: vivado -mode batch -source util_cpack2_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2/vivado.jou -#----------------------------------------------------------- -source util_cpack2_ip.tcl diff --git a/adi_library/util_pack/util_cpack2/vivado.log b/adi_library/util_pack/util_cpack2/vivado.log deleted file mode 100644 index 10e91192..00000000 --- a/adi_library/util_pack/util_cpack2/vivado.log +++ /dev/null @@ -1,1098 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:23:44 2021 -# Process ID: 66943 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2 -# Command line: vivado -mode batch -source util_cpack2_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2/vivado.jou -#----------------------------------------------------------- -source util_cpack2_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_cpack2 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_cpack2 [list \ -# "../../common/ad_perfect_shuffle.v" \ -# "../util_pack_common/pack_ctrl.v" \ -# "../util_pack_common/pack_interconnect.v" \ -# "../util_pack_common/pack_network.v" \ -# "../util_pack_common/pack_shell.v" \ -# "util_cpack2_impl.v" \ -# "util_cpack2.v" ] -# adi_ip_properties_lite util_cpack2 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_ctrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_interconnect.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_network.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_shell.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_ctrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_interconnect.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_network.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_shell.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_cpack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'enable' has a dependency on the module local parameter or undefined parameter 'REAL_NUM_OF_CHANNELS'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'fifo_wr_data' has a dependency on the module local parameter or undefined parameter 'CHANNEL_DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'fifo_wr_data' has a dependency on the module local parameter or undefined parameter 'REAL_NUM_OF_CHANNELS'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'fifo_wr_data_s' has a dependency on the module local parameter or undefined parameter 'CHANNEL_DATA_WIDTH'. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_10'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_11'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_12'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_13'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_14'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_15'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_16'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_17'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_18'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_19'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_20'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_21'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_22'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_23'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_24'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_25'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_26'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_27'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_28'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_29'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_30'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_31'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_32'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_33'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_34'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_35'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_36'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_37'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_38'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_39'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_40'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_41'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_42'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_43'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_44'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_45'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_46'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_47'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_48'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_49'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_50'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_51'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_52'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_53'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_54'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_55'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_56'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_57'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_58'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_59'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_60'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_61'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_62'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_63'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_8'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_9'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'packed_fifo_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_10'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_11'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_12'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_13'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_14'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_15'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_16'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_17'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_18'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_19'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_20'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_21'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_22'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_23'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_24'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_25'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_26'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_27'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_28'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_29'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_30'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_31'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_32'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_33'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_34'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_35'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_36'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_37'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_38'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_39'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_wr_40'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [Common 17-14] Message 'IP_Flow 19-5150' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "packed_fifo_wr" "master" \ -# "analog.com:interface:fifo_wr_rtl:1.0" \ -# "analog.com:interface:fifo_wr:1.0" \ -# { \ -# {"packed_fifo_wr_en" "EN"} \ -# {"packed_fifo_wr_data" "DATA"} \ -# {"packed_fifo_wr_overflow" "OVERFLOW"} \ -# {"packed_fifo_wr_sync" "SYNC"} \ -# } -# adi_add_bus_clock "clk" "packed_fifo_wr" "reset" -# set cc [ipx::current_core] -# for {set i 1} {$i < 64} {incr i} { -# set_property enablement_dependency "spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i" \ -# [ipx::get_ports *_$i -of_objects $cc] -# } -# foreach {k v} { \ -# "NUM_OF_CHANNELS" "Number of Channels" \ -# "SAMPLES_PER_CHANNEL" "Samples per Channel" \ -# "SAMPLE_DATA_WIDTH" "Sample Width" \ -# } { \ -# set p [ipgui::get_guiparamspec -name $k -component $cc] -# # ipgui::move_param -component $cc -order $i $p -parent $ -# set_property -dict [list \ -# DISPLAY_NAME $v \ -# ] $p -# incr i -# } -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:23:54 2021... diff --git a/adi_library/util_pack/util_upack2/util_upack2_ip.log b/adi_library/util_pack/util_upack2/util_upack2_ip.log deleted file mode 100644 index d64d7c0f..00000000 --- a/adi_library/util_pack/util_upack2/util_upack2_ip.log +++ /dev/null @@ -1,1157 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_upack2_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_upack2 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_upack2 [list \ -# "../../common/ad_perfect_shuffle.v" \ -# "../util_pack_common/pack_ctrl.v" \ -# "../util_pack_common/pack_interconnect.v" \ -# "../util_pack_common/pack_network.v" \ -# "../util_pack_common/pack_shell.v" \ -# "util_upack2_impl.v" \ -# "util_upack2.v" ] -# adi_ip_properties_lite util_upack2 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_ctrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_interconnect.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_network.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_shell.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_ctrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_interconnect.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_network.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_shell.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'fifo_rd_data' has a dependency on the module local parameter or undefined parameter 'CHANNEL_DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'fifo_rd_data' has a dependency on the module local parameter or undefined parameter 'REAL_NUM_OF_CHANNELS'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'fifo_rd_data_s' has a dependency on the module local parameter or undefined parameter 'CHANNEL_DATA_WIDTH'. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_10'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_11'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_12'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_13'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_14'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_15'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_16'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_17'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_18'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_19'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_20'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_21'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_22'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_23'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_24'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_25'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_26'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_27'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_28'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_29'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_30'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_31'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_32'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_33'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_34'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_35'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_36'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_37'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_38'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_39'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_40'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_41'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_42'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_43'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_44'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_45'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_46'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_47'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_48'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_49'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_50'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_51'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_52'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_53'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_54'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_55'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_56'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_57'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_58'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_59'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_60'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_61'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_62'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_63'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_8'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_9'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((((2 ** spirit:ceil(spirit:log(2,NUM_OF_CHANNELS))) * SAMPLE_DATA_WIDTH) * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 's_axis'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_10'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_11'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_12'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_13'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_14'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_15'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_16'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_17'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_18'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_19'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_20'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_21'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_22'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_23'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_24'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_25'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_26'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_27'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_28'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_29'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_30'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_31'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_32'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_33'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_34'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_35'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_36'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_37'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_38'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_39'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [Common 17-14] Message 'IP_Flow 19-5150' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_16' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_17' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_18' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_19' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_20' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_21' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_22' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_23' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_24' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_25' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_26' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_27' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_28' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_29' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_30' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_31' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_32' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_33' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_34' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_35' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_36' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_37' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_38' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_39' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_40' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_41' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_42' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_43' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_44' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_45' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_46' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_47' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_48' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_49' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_50' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_51' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_52' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_53' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_54' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_55' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_56' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_57' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_58' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_59' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_60' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_61' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_62' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_63' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "s_axis" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"s_axis_ready" "TREADY"} \ -# {"s_axis_valid" "TVALID"} \ -# {"s_axis_data" "TDATA"} \ -# ] -# adi_add_bus_clock "clk" "s_axis" "reset" -# set cc [ipx::current_core] -# for {set i 1} {$i < 64} {incr i} { -# set_property enablement_dependency "spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i" \ -# [ipx::get_ports *_$i -of_objects $cc] -# } -# foreach {k v} { \ -# "NUM_OF_CHANNELS" "Number of Channels" \ -# "SAMPLES_PER_CHANNEL" "Samples per Channel" \ -# "SAMPLE_DATA_WIDTH" "Sample Width" \ -# } { \ -# set p [ipgui::get_guiparamspec -name $k -component $cc] -# # ipgui::move_param -component $cc -order $i $p -parent $ -# set_property -dict [list \ -# DISPLAY_NAME $v \ -# ] $p -# incr i -# } -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:24:05 2021... diff --git a/adi_library/util_pack/util_upack2/vivado.jou b/adi_library/util_pack/util_upack2/vivado.jou deleted file mode 100644 index 455e6f49..00000000 --- a/adi_library/util_pack/util_upack2/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:23:55 2021 -# Process ID: 67008 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2 -# Command line: vivado -mode batch -source util_upack2_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2/vivado.jou -#----------------------------------------------------------- -source util_upack2_ip.tcl diff --git a/adi_library/util_pack/util_upack2/vivado.log b/adi_library/util_pack/util_upack2/vivado.log deleted file mode 100644 index 14162b47..00000000 --- a/adi_library/util_pack/util_upack2/vivado.log +++ /dev/null @@ -1,1162 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:23:55 2021 -# Process ID: 67008 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2 -# Command line: vivado -mode batch -source util_upack2_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2/vivado.jou -#----------------------------------------------------------- -source util_upack2_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_upack2 -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_upack2 [list \ -# "../../common/ad_perfect_shuffle.v" \ -# "../util_pack_common/pack_ctrl.v" \ -# "../util_pack_common/pack_interconnect.v" \ -# "../util_pack_common/pack_network.v" \ -# "../util_pack_common/pack_shell.v" \ -# "util_upack2_impl.v" \ -# "util_upack2.v" ] -# adi_ip_properties_lite util_upack2 -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_ctrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_interconnect.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_network.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_shell.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_ctrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_interconnect.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_network.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_pack_common/pack_shell.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'fifo_rd_data' has a dependency on the module local parameter or undefined parameter 'CHANNEL_DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'fifo_rd_data' has a dependency on the module local parameter or undefined parameter 'REAL_NUM_OF_CHANNELS'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'fifo_rd_data_s' has a dependency on the module local parameter or undefined parameter 'CHANNEL_DATA_WIDTH'. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_10'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_11'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_12'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_13'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_14'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_15'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_16'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_17'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_18'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_19'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_20'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_21'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_22'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_23'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_24'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_25'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_26'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_27'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_28'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_29'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_30'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_31'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_32'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_33'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_34'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_35'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_36'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_37'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_38'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_39'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_40'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_41'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_42'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_43'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_44'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_45'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_46'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_47'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_48'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_49'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_50'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_51'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_52'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_53'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_54'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_55'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_56'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_57'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_58'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_59'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_60'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_61'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_62'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_63'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_8'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_9'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((((2 ** spirit:ceil(spirit:log(2,NUM_OF_CHANNELS))) * SAMPLE_DATA_WIDTH) * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 's_axis'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_32' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_33' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_34' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_35' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_36' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_37' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_38' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_39' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_40' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_41' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_42' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_43' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_44' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_45' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_46' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_47' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_48' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_49' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_50' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_51' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_52' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_53' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_54' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_55' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_56' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_57' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_58' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_59' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_60' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_61' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_62' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_63' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_10'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_11'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_12'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_13'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_14'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_15'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_16'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_17'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_18'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_19'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_20'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_21'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_22'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_23'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_24'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_25'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_26'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_27'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_28'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_29'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_30'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_31'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_32'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_33'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_34'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_35'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_36'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_37'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_38'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_39'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '((SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL) - 1):0' is present in all ports of the interface 'fifo_rd_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [Common 17-14] Message 'IP_Flow 19-5150' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_16' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_17' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_18' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_19' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_20' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_21' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_22' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_23' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_24' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_25' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_26' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_27' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_28' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_29' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_30' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_31' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_32' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_32': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_33' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_33': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_34' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_34': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_35' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_35': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_36' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_36': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_37' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_37': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_38' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_38': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_39' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_39': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_40' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_40': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_41' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_41': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_42' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_42': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_43' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_43': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_44' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_44': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_45' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_45': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_46' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_46': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_47' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_47': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_48' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_48': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_49' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_49': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_50' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_50': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_51' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_51': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_52' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_52': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_53' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_53': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_54' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_54': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_55' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_55': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_56' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_56': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_57' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_57': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_58' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_58': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_59' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_59': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_60' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_60': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_61' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_61': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_62' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_62': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_63' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_63': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'fifo_rd_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "s_axis" "slave" \ -# "xilinx.com:interface:axis_rtl:1.0" \ -# "xilinx.com:interface:axis:1.0" \ -# [list {"s_axis_ready" "TREADY"} \ -# {"s_axis_valid" "TVALID"} \ -# {"s_axis_data" "TDATA"} \ -# ] -# adi_add_bus_clock "clk" "s_axis" "reset" -# set cc [ipx::current_core] -# for {set i 1} {$i < 64} {incr i} { -# set_property enablement_dependency "spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i" \ -# [ipx::get_ports *_$i -of_objects $cc] -# } -# foreach {k v} { \ -# "NUM_OF_CHANNELS" "Number of Channels" \ -# "SAMPLES_PER_CHANNEL" "Samples per Channel" \ -# "SAMPLE_DATA_WIDTH" "Sample Width" \ -# } { \ -# set p [ipgui::get_guiparamspec -name $k -component $cc] -# # ipgui::move_param -component $cc -order $i $p -parent $ -# set_property -dict [list \ -# DISPLAY_NAME $v \ -# ] $p -# incr i -# } -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:24:05 2021... diff --git a/adi_library/util_pulse_gen/util_pulse_gen_ip.log b/adi_library/util_pulse_gen/util_pulse_gen_ip.log deleted file mode 100644 index 647f896f..00000000 --- a/adi_library/util_pulse_gen/util_pulse_gen_ip.log +++ /dev/null @@ -1,695 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_pulse_gen_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_pulse_gen -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pulse_gen'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_pulse_gen [list \ -# "$ad_hdl_dir/library/common/util_pulse_gen.v"] -# adi_ip_properties_lite util_pulse_gen -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rstn'. -WARNING: [IP_Flow 19-3157] Bus Interface 'rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rstn'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:40 2021... diff --git a/adi_library/util_pulse_gen/vivado.jou b/adi_library/util_pulse_gen/vivado.jou deleted file mode 100644 index 809cd547..00000000 --- a/adi_library/util_pulse_gen/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:33 2021 -# Process ID: 7777 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pulse_gen -# Command line: vivado -mode batch -source util_pulse_gen_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pulse_gen/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pulse_gen/vivado.jou -#----------------------------------------------------------- -source util_pulse_gen_ip.tcl diff --git a/adi_library/util_pulse_gen/vivado.log b/adi_library/util_pulse_gen/vivado.log deleted file mode 100644 index 3de7577c..00000000 --- a/adi_library/util_pulse_gen/vivado.log +++ /dev/null @@ -1,700 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:33 2021 -# Process ID: 7777 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pulse_gen -# Command line: vivado -mode batch -source util_pulse_gen_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pulse_gen/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pulse_gen/vivado.jou -#----------------------------------------------------------- -source util_pulse_gen_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_pulse_gen -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pulse_gen'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_pulse_gen [list \ -# "$ad_hdl_dir/library/common/util_pulse_gen.v"] -# adi_ip_properties_lite util_pulse_gen -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pulse_gen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rstn'. -WARNING: [IP_Flow 19-3157] Bus Interface 'rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rstn'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:40 2021... diff --git a/adi_library/util_rfifo/util_rfifo_ip.log b/adi_library/util_rfifo/util_rfifo_ip.log deleted file mode 100644 index 2ffb8386..00000000 --- a/adi_library/util_rfifo/util_rfifo_ip.log +++ /dev/null @@ -1,925 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_rfifo_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_rfifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_rfifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_rfifo [list \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "util_rfifo_constr.xdc" \ -# "util_rfifo.v" ] -# adi_ip_properties_lite util_rfifo -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_rfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_rfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'din_wdata' has a dependency on the module local parameter or undefined parameter 'DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'din_waddr' has a dependency on the module local parameter or undefined parameter 'ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_data' has a dependency on the module local parameter or undefined parameter 'T_DOUT_DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_rdata' has a dependency on the module local parameter or undefined parameter 'DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_raddr' has a dependency on the module local parameter or undefined parameter 'ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'din_data_s' has a dependency on the module local parameter or undefined parameter 'T_DIN_DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_data_s' has a dependency on the module local parameter or undefined parameter 'T_DOUT_DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_rdata_s' has a dependency on the module local parameter or undefined parameter 'DATA_WIDTH'. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_2' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_3' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_4' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_5' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_6' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_7' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_2' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_3' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_4' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_5' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_6' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_7' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'din_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'din_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'din_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 'dout_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dout_rst'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_0' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_1' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_2' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_3' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_4' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_4': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_5' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_5': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_6' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_6': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_7' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_7': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_4': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_5': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_6': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_7': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3157] Bus Interface 'din_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'din_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'din_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dout_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# set_property driver_value 0 [ipx::get_ports *dout_enable* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dout_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *din_valid_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *din_unf* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \ -# [ipx::get_ports *_1* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \ -# [ipx::get_ports *_2* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \ -# [ipx::get_ports *_3* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \ -# [ipx::get_ports *_4* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \ -# [ipx::get_ports *_5* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \ -# [ipx::get_ports *_6* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \ -# [ipx::get_ports *_7* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface din_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dout_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface din_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'din_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'din_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'din_rstn'. -# ipx::infer_bus_interface dout_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dout_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dout_rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:24:13 2021... diff --git a/adi_library/util_rfifo/vivado.jou b/adi_library/util_rfifo/vivado.jou deleted file mode 100644 index 97cf029e..00000000 --- a/adi_library/util_rfifo/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:24:06 2021 -# Process ID: 67072 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_rfifo -# Command line: vivado -mode batch -source util_rfifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_rfifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_rfifo/vivado.jou -#----------------------------------------------------------- -source util_rfifo_ip.tcl diff --git a/adi_library/util_rfifo/vivado.log b/adi_library/util_rfifo/vivado.log deleted file mode 100644 index ee3d7b2e..00000000 --- a/adi_library/util_rfifo/vivado.log +++ /dev/null @@ -1,930 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:24:06 2021 -# Process ID: 67072 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_rfifo -# Command line: vivado -mode batch -source util_rfifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_rfifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_rfifo/vivado.jou -#----------------------------------------------------------- -source util_rfifo_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_rfifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_rfifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_rfifo [list \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "util_rfifo_constr.xdc" \ -# "util_rfifo.v" ] -# adi_ip_properties_lite util_rfifo -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_rfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_rfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'din_wdata' has a dependency on the module local parameter or undefined parameter 'DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'din_waddr' has a dependency on the module local parameter or undefined parameter 'ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_data' has a dependency on the module local parameter or undefined parameter 'T_DOUT_DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_rdata' has a dependency on the module local parameter or undefined parameter 'DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_raddr' has a dependency on the module local parameter or undefined parameter 'ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'din_data_s' has a dependency on the module local parameter or undefined parameter 'T_DIN_DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_data_s' has a dependency on the module local parameter or undefined parameter 'T_DOUT_DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_rdata_s' has a dependency on the module local parameter or undefined parameter 'DATA_WIDTH'. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_2' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_3' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_4' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_5' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_6' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_in_7' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_2' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_3' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_4' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_5' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_6' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_out_7' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'din_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'din_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'din_rstn'. -INFO: [IP_Flow 19-4728] Bus Interface 'dout_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dout_rst'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_0' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_1' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_2' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_3' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_4' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_4': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_5' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_5': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_6' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_6': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'din_valid_in_7' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_7': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_in_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_0': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_1': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_2': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_3': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_4': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_5': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_6': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_7': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_out_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3157] Bus Interface 'din_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'din_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'din_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dout_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# set_property driver_value 0 [ipx::get_ports *dout_enable* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dout_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *din_valid_in* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *din_unf* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \ -# [ipx::get_ports *_1* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \ -# [ipx::get_ports *_2* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \ -# [ipx::get_ports *_3* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \ -# [ipx::get_ports *_4* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \ -# [ipx::get_ports *_5* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \ -# [ipx::get_ports *_6* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \ -# [ipx::get_ports *_7* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface din_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dout_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface din_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'din_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'din_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'din_rstn'. -# ipx::infer_bus_interface dout_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dout_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dout_rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:24:13 2021... diff --git a/adi_library/util_sigma_delta_spi/util_sigma_delta_spi_ip.log b/adi_library/util_sigma_delta_spi/util_sigma_delta_spi_ip.log deleted file mode 100644 index a87a054a..00000000 --- a/adi_library/util_sigma_delta_spi/util_sigma_delta_spi_ip.log +++ /dev/null @@ -1,709 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_sigma_delta_spi_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_sigma_delta_spi -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_sigma_delta_spi'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_sigma_delta_spi [list \ -# "util_sigma_delta_spi.v" \ -# ] -# adi_ip_properties_lite util_sigma_delta_spi -INFO: [IP_Flow 19-5107] Inferred bus interface 'm' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 's' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "m_spi" "master" \ -# "analog.com:interface:spi_master_rtl:1.0" \ -# "analog.com:interface:spi_master:1.0" \ -# { -# {"m_sclk" "SCLK"} \ -# {"m_sdi" "SDI"} \ -# {"m_sdo" "SDO"} \ -# {"m_sdo_t" "SDO_T"} \ -# {"m_cs" "CS"} \ -# } -# adi_add_bus "s_spi" "slave" \ -# "analog.com:interface:spi_master_rtl:1.0" \ -# "analog.com:interface:spi_master:1.0" \ -# { -# {"s_sclk" "SCLK"} \ -# {"s_sdi" "SDI"} \ -# {"s_sdo" "SDO"} \ -# {"s_sdo_t" "SDO_T"} \ -# {"s_cs" "CS"} \ -# } -# adi_add_bus_clock "clk" "m_spi:s_spi" "resetn" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:47 2021... diff --git a/adi_library/util_sigma_delta_spi/vivado.jou b/adi_library/util_sigma_delta_spi/vivado.jou deleted file mode 100644 index 257a0cc5..00000000 --- a/adi_library/util_sigma_delta_spi/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:40 2021 -# Process ID: 7835 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_sigma_delta_spi -# Command line: vivado -mode batch -source util_sigma_delta_spi_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_sigma_delta_spi/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_sigma_delta_spi/vivado.jou -#----------------------------------------------------------- -source util_sigma_delta_spi_ip.tcl diff --git a/adi_library/util_sigma_delta_spi/vivado.log b/adi_library/util_sigma_delta_spi/vivado.log deleted file mode 100644 index 4e243d79..00000000 --- a/adi_library/util_sigma_delta_spi/vivado.log +++ /dev/null @@ -1,714 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:40 2021 -# Process ID: 7835 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_sigma_delta_spi -# Command line: vivado -mode batch -source util_sigma_delta_spi_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_sigma_delta_spi/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_sigma_delta_spi/vivado.jou -#----------------------------------------------------------- -source util_sigma_delta_spi_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_sigma_delta_spi -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_sigma_delta_spi'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_sigma_delta_spi [list \ -# "util_sigma_delta_spi.v" \ -# ] -# adi_ip_properties_lite util_sigma_delta_spi -INFO: [IP_Flow 19-5107] Inferred bus interface 'm' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 's' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_add_bus "m_spi" "master" \ -# "analog.com:interface:spi_master_rtl:1.0" \ -# "analog.com:interface:spi_master:1.0" \ -# { -# {"m_sclk" "SCLK"} \ -# {"m_sdi" "SDI"} \ -# {"m_sdo" "SDO"} \ -# {"m_sdo_t" "SDO_T"} \ -# {"m_cs" "CS"} \ -# } -# adi_add_bus "s_spi" "slave" \ -# "analog.com:interface:spi_master_rtl:1.0" \ -# "analog.com:interface:spi_master:1.0" \ -# { -# {"s_sclk" "SCLK"} \ -# {"s_sdi" "SDI"} \ -# {"s_sdo" "SDO"} \ -# {"s_sdo_t" "SDO_T"} \ -# {"s_cs" "CS"} \ -# } -# adi_add_bus_clock "clk" "m_spi:s_spi" "resetn" -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:47 2021... diff --git a/adi_library/util_tdd_sync/util_tdd_sync_ip.log b/adi_library/util_tdd_sync/util_tdd_sync_ip.log deleted file mode 100644 index bab0b9d8..00000000 --- a/adi_library/util_tdd_sync/util_tdd_sync_ip.log +++ /dev/null @@ -1,696 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_tdd_sync_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_tdd_sync -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_tdd_sync'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_tdd_sync [list \ -# "$ad_hdl_dir/library/common/util_pulse_gen.v" \ -# "util_tdd_sync_constr.xdc" \ -# "util_tdd_sync.v"] -# adi_ip_properties_lite util_tdd_sync -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_tdd_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_tdd_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rstn'. -WARNING: [IP_Flow 19-3157] Bus Interface 'rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rstn'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:24:21 2021... diff --git a/adi_library/util_tdd_sync/vivado.jou b/adi_library/util_tdd_sync/vivado.jou deleted file mode 100644 index 4fec134b..00000000 --- a/adi_library/util_tdd_sync/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:24:14 2021 -# Process ID: 67126 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_tdd_sync -# Command line: vivado -mode batch -source util_tdd_sync_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_tdd_sync/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_tdd_sync/vivado.jou -#----------------------------------------------------------- -source util_tdd_sync_ip.tcl diff --git a/adi_library/util_tdd_sync/vivado.log b/adi_library/util_tdd_sync/vivado.log deleted file mode 100644 index 3d58e962..00000000 --- a/adi_library/util_tdd_sync/vivado.log +++ /dev/null @@ -1,701 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:24:14 2021 -# Process ID: 67126 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_tdd_sync -# Command line: vivado -mode batch -source util_tdd_sync_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_tdd_sync/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_tdd_sync/vivado.jou -#----------------------------------------------------------- -source util_tdd_sync_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_tdd_sync -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_tdd_sync'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_tdd_sync [list \ -# "$ad_hdl_dir/library/common/util_pulse_gen.v" \ -# "util_tdd_sync_constr.xdc" \ -# "util_tdd_sync.v"] -# adi_ip_properties_lite util_tdd_sync -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_tdd_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/util_pulse_gen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_tdd_sync'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rstn'. -WARNING: [IP_Flow 19-3157] Bus Interface 'rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rstn'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:24:21 2021... diff --git a/adi_library/util_var_fifo/util_var_fifo_ip.log b/adi_library/util_var_fifo/util_var_fifo_ip.log deleted file mode 100644 index 1a591571..00000000 --- a/adi_library/util_var_fifo/util_var_fifo_ip.log +++ /dev/null @@ -1,702 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_var_fifo_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_var_fifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_var_fifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_var_fifo [list \ -# "util_var_fifo.v" ] -# adi_ip_properties_lite util_var_fifo -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data_in' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data_out' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rst'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data_in_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:55 2021... diff --git a/adi_library/util_var_fifo/vivado.jou b/adi_library/util_var_fifo/vivado.jou deleted file mode 100644 index 4d9c4666..00000000 --- a/adi_library/util_var_fifo/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:48 2021 -# Process ID: 7891 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_var_fifo -# Command line: vivado -mode batch -source util_var_fifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_var_fifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_var_fifo/vivado.jou -#----------------------------------------------------------- -source util_var_fifo_ip.tcl diff --git a/adi_library/util_var_fifo/vivado.log b/adi_library/util_var_fifo/vivado.log deleted file mode 100644 index fd7706b2..00000000 --- a/adi_library/util_var_fifo/vivado.log +++ /dev/null @@ -1,707 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:48 2021 -# Process ID: 7891 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_var_fifo -# Command line: vivado -mode batch -source util_var_fifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_var_fifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_var_fifo/vivado.jou -#----------------------------------------------------------- -source util_var_fifo_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_var_fifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_var_fifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_var_fifo [list \ -# "util_var_fifo.v" ] -# adi_ip_properties_lite util_var_fifo -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data_in' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'data_out' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rst'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'data_in_valid' and definition port 'VALID'. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'data_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:19:55 2021... diff --git a/adi_library/util_wfifo/util_wfifo_ip.log b/adi_library/util_wfifo/util_wfifo_ip.log deleted file mode 100644 index 6020b711..00000000 --- a/adi_library/util_wfifo/util_wfifo_ip.log +++ /dev/null @@ -1,821 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_wfifo_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_wfifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_wfifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_wfifo [list \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "util_wfifo_constr.xdc" \ -# "util_wfifo.v" ] -# adi_ip_properties_lite util_wfifo -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_wfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_wfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'din_wdata' has a dependency on the module local parameter or undefined parameter 'DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'din_waddr' has a dependency on the module local parameter or undefined parameter 'ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'din_rinit' has a dependency on the module local parameter or undefined parameter 'ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_rinit' has a dependency on the module local parameter or undefined parameter 'ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_raddr' has a dependency on the module local parameter or undefined parameter 'ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_rdata' has a dependency on the module local parameter or undefined parameter 'DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'din_data_s' has a dependency on the module local parameter or undefined parameter 'T_DIN_DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_rdata_s' has a dependency on the module local parameter or undefined parameter 'DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_data_s' has a dependency on the module local parameter or undefined parameter 'T_DOUT_DATA_WIDTH'. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'dout_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'din_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'din_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'dout_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dout_rstn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3157] Bus Interface 'dout_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'dout_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'din_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dout_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# set_property driver_value 0 [ipx::get_ports *din_enable* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *din_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dout_ovf* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \ -# [ipx::get_ports *_1* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \ -# [ipx::get_ports *_2* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \ -# [ipx::get_ports *_3* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \ -# [ipx::get_ports *_4* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \ -# [ipx::get_ports *_5* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \ -# [ipx::get_ports *_6* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \ -# [ipx::get_ports *_7* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface din_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface din_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'din_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'din_rst'. -# ipx::infer_bus_interface dout_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dout_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dout_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'dout_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dout_rstn'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:24:29 2021... diff --git a/adi_library/util_wfifo/vivado.jou b/adi_library/util_wfifo/vivado.jou deleted file mode 100644 index dd695b07..00000000 --- a/adi_library/util_wfifo/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:24:22 2021 -# Process ID: 67182 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_wfifo -# Command line: vivado -mode batch -source util_wfifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_wfifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_wfifo/vivado.jou -#----------------------------------------------------------- -source util_wfifo_ip.tcl diff --git a/adi_library/util_wfifo/vivado.log b/adi_library/util_wfifo/vivado.log deleted file mode 100644 index 0315e445..00000000 --- a/adi_library/util_wfifo/vivado.log +++ /dev/null @@ -1,826 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:24:22 2021 -# Process ID: 67182 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_wfifo -# Command line: vivado -mode batch -source util_wfifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_wfifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_wfifo/vivado.jou -#----------------------------------------------------------- -source util_wfifo_ip.tcl -# source ../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_wfifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_wfifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_wfifo [list \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "util_wfifo_constr.xdc" \ -# "util_wfifo.v" ] -# adi_ip_properties_lite util_wfifo -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_wfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_wfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'din_wdata' has a dependency on the module local parameter or undefined parameter 'DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'din_waddr' has a dependency on the module local parameter or undefined parameter 'ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'din_rinit' has a dependency on the module local parameter or undefined parameter 'ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_rinit' has a dependency on the module local parameter or undefined parameter 'ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_raddr' has a dependency on the module local parameter or undefined parameter 'ADDRESS_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_rdata' has a dependency on the module local parameter or undefined parameter 'DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'din_data_s' has a dependency on the module local parameter or undefined parameter 'T_DIN_DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_rdata_s' has a dependency on the module local parameter or undefined parameter 'DATA_WIDTH'. -WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dout_data_s' has a dependency on the module local parameter or undefined parameter 'T_DOUT_DATA_WIDTH'. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DIN_DATA_WIDTH - 1):0' is present in all ports of the interface 'din_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_0'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_1'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_2'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_3'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_4'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_5'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_6'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DOUT_DATA_WIDTH - 1):0' is present in all ports of the interface 'dout_7'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'dout_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'din_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'din_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'dout_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dout_rstn'. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'din_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dout_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dout_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3157] Bus Interface 'dout_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'dout_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'din_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dout_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::remove_all_bus_interface [ipx::current_core] -# set_property driver_value 0 [ipx::get_ports *din_enable* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *din_valid* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]] -# set_property driver_value 0 [ipx::get_ports *dout_ovf* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \ -# [ipx::get_ports *_1* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \ -# [ipx::get_ports *_2* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \ -# [ipx::get_ports *_3* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \ -# [ipx::get_ports *_4* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \ -# [ipx::get_ports *_5* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \ -# [ipx::get_ports *_6* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \ -# [ipx::get_ports *_7* -of_objects [ipx::current_core]] -# ipx::infer_bus_interface din_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface din_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'din_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'din_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'din_rst'. -# ipx::infer_bus_interface dout_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dout_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dout_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dout_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'dout_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dout_rstn'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:24:29 2021... diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_ip.log b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_ip.log deleted file mode 100644 index b0dcf3c3..00000000 --- a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_ip.log +++ /dev/null @@ -1,811 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_adcfifo_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_adcfifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_adcfifo [list \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "$ad_hdl_dir/library/common/ad_mem_asym.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \ -# "axi_adcfifo_adc.v" \ -# "axi_adcfifo_dma.v" \ -# "axi_adcfifo_wr.v" \ -# "axi_adcfifo_rd.v" \ -# "axi_adcfifo.v" \ -# "axi_adcfifo_constr.xdc" ] -# adi_ip_properties_lite axi_adcfifo -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port rdata on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(ADC_DATA_WIDTH - 1):0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_xfer_req' and definition port 'XFER_REQ'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "rdata" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'axi_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::infer_bus_interface {\ -# axi_awvalid \ -# axi_awid \ -# axi_awburst \ -# axi_awlock \ -# axi_awcache \ -# axi_awprot \ -# axi_awqos \ -# axi_awuser \ -# axi_awlen \ -# axi_awsize \ -# axi_awaddr \ -# axi_awready \ -# axi_wvalid \ -# axi_wdata \ -# axi_wstrb \ -# axi_wlast \ -# axi_wuser \ -# axi_wready \ -# axi_bvalid \ -# axi_bid \ -# axi_bresp \ -# axi_buser \ -# axi_bready \ -# axi_arvalid \ -# axi_arid \ -# axi_arburst \ -# axi_arlock \ -# axi_arcache \ -# axi_arprot \ -# axi_arqos \ -# axi_aruser \ -# axi_arlen \ -# axi_arsize \ -# axi_araddr \ -# axi_arready \ -# axi_rvalid \ -# axi_rid \ -# axi_ruser \ -# axi_rresp \ -# axi_rlast \ -# axi_rdata \ -# axi_rready} \ -# xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -# ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'axi'. -# ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'. -# ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \ -# -of_objects [ipx::current_core]] -# set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ -# -of_objects [ipx::get_bus_interfaces axi_clk \ -# -of_objects [ipx::current_core]]] -# ipx::add_address_space axi [ipx::current_core] -# set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \ -# -of_objects [ipx::current_core]] -# set_property range 4294967296 [ipx::get_address_spaces axi \ -# -of_objects [ipx::current_core]] -# set_property width 512 [ipx::get_address_spaces axi \ -# -of_objects [ipx::current_core]] -# ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:20:07 2021... diff --git a/adi_library/xilinx/axi_adcfifo/vivado.jou b/adi_library/xilinx/axi_adcfifo/vivado.jou deleted file mode 100644 index 84ee2054..00000000 --- a/adi_library/xilinx/axi_adcfifo/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:55 2021 -# Process ID: 7949 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo -# Command line: vivado -mode batch -source axi_adcfifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo/vivado.jou -#----------------------------------------------------------- -source axi_adcfifo_ip.tcl diff --git a/adi_library/xilinx/axi_adcfifo/vivado.log b/adi_library/xilinx/axi_adcfifo/vivado.log deleted file mode 100644 index 3ed9a901..00000000 --- a/adi_library/xilinx/axi_adcfifo/vivado.log +++ /dev/null @@ -1,816 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:19:55 2021 -# Process ID: 7949 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo -# Command line: vivado -mode batch -source axi_adcfifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo/vivado.jou -#----------------------------------------------------------- -source axi_adcfifo_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_adcfifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_adcfifo [list \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "$ad_hdl_dir/library/common/ad_mem_asym.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \ -# "axi_adcfifo_adc.v" \ -# "axi_adcfifo_dma.v" \ -# "axi_adcfifo_wr.v" \ -# "axi_adcfifo_rd.v" \ -# "axi_adcfifo.v" \ -# "axi_adcfifo_constr.xdc" ] -# adi_ip_properties_lite axi_adcfifo -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port rdata on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(ADC_DATA_WIDTH - 1):0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_xfer_req' and definition port 'XFER_REQ'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "rdata" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'axi_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::infer_bus_interface {\ -# axi_awvalid \ -# axi_awid \ -# axi_awburst \ -# axi_awlock \ -# axi_awcache \ -# axi_awprot \ -# axi_awqos \ -# axi_awuser \ -# axi_awlen \ -# axi_awsize \ -# axi_awaddr \ -# axi_awready \ -# axi_wvalid \ -# axi_wdata \ -# axi_wstrb \ -# axi_wlast \ -# axi_wuser \ -# axi_wready \ -# axi_bvalid \ -# axi_bid \ -# axi_bresp \ -# axi_buser \ -# axi_bready \ -# axi_arvalid \ -# axi_arid \ -# axi_arburst \ -# axi_arlock \ -# axi_arcache \ -# axi_arprot \ -# axi_arqos \ -# axi_aruser \ -# axi_arlen \ -# axi_arsize \ -# axi_araddr \ -# axi_arready \ -# axi_rvalid \ -# axi_rid \ -# axi_ruser \ -# axi_rresp \ -# axi_rlast \ -# axi_rdata \ -# axi_rready} \ -# xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -# ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'axi'. -# ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'. -# ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \ -# -of_objects [ipx::current_core]] -# set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ -# -of_objects [ipx::get_bus_interfaces axi_clk \ -# -of_objects [ipx::current_core]]] -# ipx::add_address_space axi [ipx::current_core] -# set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \ -# -of_objects [ipx::current_core]] -# set_property range 4294967296 [ipx::get_address_spaces axi \ -# -of_objects [ipx::current_core]] -# set_property width 512 [ipx::get_address_spaces axi \ -# -of_objects [ipx::current_core]] -# ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:20:07 2021... diff --git a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_ip.log b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_ip.log deleted file mode 100644 index 94feca15..00000000 --- a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_ip.log +++ /dev/null @@ -1,2995 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_adxcvr_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_adxcvr -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_adxcvr [list \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \ -# "axi_adxcvr_es.v" \ -# "axi_adxcvr_up.v" \ -# "axi_adxcvr_mdrp.v" \ -# "axi_adxcvr_mstatus.v" \ -# "axi_adxcvr.v" ] -# adi_ip_properties axi_adxcvr -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_cm_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_cm_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_cm_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_cm_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_cm_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_cm_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_cm_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_cm_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_es_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_es_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_es_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_es_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [Common 17-14] Message 'IP_Flow 19-5151' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3158] Bus Interface 'm_axi': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Synthesis'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Simulation'. -Resolution: Remove the file from the specified file group. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_infer_mm_interfaces axi_adxcvr -INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'. -INFO: [IP_Flow 19-3164] Bus Interface 'm_axi': References existing address space 'm_axi'. -# adi_init_bd_tcl -# adi_ip_bd axi_adxcvr "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] -# set_property master_address_space_ref m_axi \ -# [ipx::get_bus_interfaces m_axi \ -# -of_objects [ipx::current_core]] -# for {set n 0} {$n < 16} {incr n} { -# -# if {($n%4) == 0} { -# adi_if_infer_bus analog.com:interface:if_xcvr_cm master up_cm_${n} [list \ -# "enb up_cm_enb_${n} "\ -# "addr up_cm_addr_${n} "\ -# "wr up_cm_wr_${n} "\ -# "wdata up_cm_wdata_${n} "\ -# "rdata up_cm_rdata_${n} "\ -# "ready up_cm_ready_${n} "] -# } -# -# adi_if_infer_bus analog.com:interface:if_xcvr_cm master up_es_${n} [list \ -# "enb up_es_enb_${n} "\ -# "addr up_es_addr_${n} "\ -# "wr up_es_wr_${n} "\ -# "reset up_es_reset_${n} "\ -# "wdata up_es_wdata_${n} "\ -# "rdata up_es_rdata_${n} "\ -# "ready up_es_ready_${n} "] -# -# adi_if_infer_bus analog.com:interface:if_xcvr_ch master up_ch_${n} [list \ -# "pll_locked up_ch_pll_locked_${n} "\ -# "rst up_ch_rst_${n} "\ -# "user_ready up_ch_user_ready_${n} "\ -# "rst_done up_ch_rst_done_${n} "\ -# "lpm_dfe_n up_ch_lpm_dfe_n_${n} "\ -# "rate up_ch_rate_${n} "\ -# "sys_clk_sel up_ch_sys_clk_sel_${n} "\ -# "out_clk_sel up_ch_out_clk_sel_${n} "\ -# "tx_diffctrl up_ch_tx_diffctrl_${n} "\ -# "tx_postcursor up_ch_tx_postcursor_${n} "\ -# "tx_precursor up_ch_tx_precursor_${n} "\ -# "enb up_ch_enb_${n} "\ -# "addr up_ch_addr_${n} "\ -# "wr up_ch_wr_${n} "\ -# "wdata up_ch_wdata_${n} "\ -# "rdata up_ch_rdata_${n} "\ -# "ready up_ch_ready_${n} "] -# -# } -# ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -# set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ -# -of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]] -# set_property enablement_dependency \ -# {spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0} \ -# [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \ -# [ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \ -# [ipx::get_bus_interfaces up_ch_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \ -# [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1))} \ -# [ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \ -# [ipx::get_bus_interfaces up_ch_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2))} \ -# [ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \ -# [ipx::get_bus_interfaces up_ch_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3))} \ -# [ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \ -# [ipx::get_bus_interfaces up_ch_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \ -# [ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \ -# [ipx::get_bus_interfaces up_ch_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \ -# [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5))} \ -# [ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \ -# [ipx::get_bus_interfaces up_ch_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6))} \ -# [ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \ -# [ipx::get_bus_interfaces up_ch_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7))} \ -# [ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \ -# [ipx::get_bus_interfaces up_ch_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \ -# [ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8} \ -# [ipx::get_bus_interfaces up_ch_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \ -# [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9))} \ -# [ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9} \ -# [ipx::get_bus_interfaces up_ch_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10))} \ -# [ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10} \ -# [ipx::get_bus_interfaces up_ch_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11))} \ -# [ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11} \ -# [ipx::get_bus_interfaces up_ch_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \ -# [ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12} \ -# [ipx::get_bus_interfaces up_ch_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \ -# [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13))} \ -# [ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13} \ -# [ipx::get_bus_interfaces up_ch_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14))} \ -# [ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14} \ -# [ipx::get_bus_interfaces up_ch_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15))} \ -# [ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15} \ -# [ipx::get_bus_interfaces up_ch_15 -of_objects [ipx::current_core]] -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:25:35 2021... diff --git a/adi_library/xilinx/axi_adxcvr/vivado.jou b/adi_library/xilinx/axi_adxcvr/vivado.jou deleted file mode 100644 index c8a3bce6..00000000 --- a/adi_library/xilinx/axi_adxcvr/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:25:24 2021 -# Process ID: 146145 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr -# Command line: vivado -mode batch -source axi_adxcvr_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr/vivado.jou -#----------------------------------------------------------- -source axi_adxcvr_ip.tcl diff --git a/adi_library/xilinx/axi_adxcvr/vivado.log b/adi_library/xilinx/axi_adxcvr/vivado.log deleted file mode 100644 index 9149f02a..00000000 --- a/adi_library/xilinx/axi_adxcvr/vivado.log +++ /dev/null @@ -1,3000 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:25:24 2021 -# Process ID: 146145 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr -# Command line: vivado -mode batch -source axi_adxcvr_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr/vivado.jou -#----------------------------------------------------------- -source axi_adxcvr_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_adxcvr -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_adxcvr [list \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \ -# "axi_adxcvr_es.v" \ -# "axi_adxcvr_up.v" \ -# "axi_adxcvr_mdrp.v" \ -# "axi_adxcvr_mstatus.v" \ -# "axi_adxcvr.v" ] -# adi_ip_properties axi_adxcvr -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_cm_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_cm_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_cm_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_cm_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_cm_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_cm_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_cm_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_cm_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_es_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_es_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_es_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_es_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [Common 17-14] Message 'IP_Flow 19-5151' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3158] Bus Interface 'm_axi': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Synthesis'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Simulation'. -Resolution: Remove the file from the specified file group. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# adi_ip_infer_mm_interfaces axi_adxcvr -INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'. -INFO: [IP_Flow 19-3164] Bus Interface 'm_axi': References existing address space 'm_axi'. -# adi_init_bd_tcl -# adi_ip_bd axi_adxcvr "bd/bd.tcl" -# set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] -# set_property master_address_space_ref m_axi \ -# [ipx::get_bus_interfaces m_axi \ -# -of_objects [ipx::current_core]] -# for {set n 0} {$n < 16} {incr n} { -# -# if {($n%4) == 0} { -# adi_if_infer_bus analog.com:interface:if_xcvr_cm master up_cm_${n} [list \ -# "enb up_cm_enb_${n} "\ -# "addr up_cm_addr_${n} "\ -# "wr up_cm_wr_${n} "\ -# "wdata up_cm_wdata_${n} "\ -# "rdata up_cm_rdata_${n} "\ -# "ready up_cm_ready_${n} "] -# } -# -# adi_if_infer_bus analog.com:interface:if_xcvr_cm master up_es_${n} [list \ -# "enb up_es_enb_${n} "\ -# "addr up_es_addr_${n} "\ -# "wr up_es_wr_${n} "\ -# "reset up_es_reset_${n} "\ -# "wdata up_es_wdata_${n} "\ -# "rdata up_es_rdata_${n} "\ -# "ready up_es_ready_${n} "] -# -# adi_if_infer_bus analog.com:interface:if_xcvr_ch master up_ch_${n} [list \ -# "pll_locked up_ch_pll_locked_${n} "\ -# "rst up_ch_rst_${n} "\ -# "user_ready up_ch_user_ready_${n} "\ -# "rst_done up_ch_rst_done_${n} "\ -# "lpm_dfe_n up_ch_lpm_dfe_n_${n} "\ -# "rate up_ch_rate_${n} "\ -# "sys_clk_sel up_ch_sys_clk_sel_${n} "\ -# "out_clk_sel up_ch_out_clk_sel_${n} "\ -# "tx_diffctrl up_ch_tx_diffctrl_${n} "\ -# "tx_postcursor up_ch_tx_postcursor_${n} "\ -# "tx_precursor up_ch_tx_precursor_${n} "\ -# "enb up_ch_enb_${n} "\ -# "addr up_ch_addr_${n} "\ -# "wr up_ch_wr_${n} "\ -# "wdata up_ch_wdata_${n} "\ -# "rdata up_ch_rdata_${n} "\ -# "ready up_ch_ready_${n} "] -# -# } -# ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -# set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ -# -of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]] -# set_property enablement_dependency \ -# {spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0} \ -# [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \ -# [ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \ -# [ipx::get_bus_interfaces up_ch_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \ -# [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1))} \ -# [ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \ -# [ipx::get_bus_interfaces up_ch_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2))} \ -# [ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \ -# [ipx::get_bus_interfaces up_ch_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3))} \ -# [ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \ -# [ipx::get_bus_interfaces up_ch_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \ -# [ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \ -# [ipx::get_bus_interfaces up_ch_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \ -# [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5))} \ -# [ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \ -# [ipx::get_bus_interfaces up_ch_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6))} \ -# [ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \ -# [ipx::get_bus_interfaces up_ch_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7))} \ -# [ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \ -# [ipx::get_bus_interfaces up_ch_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \ -# [ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8} \ -# [ipx::get_bus_interfaces up_ch_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \ -# [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9))} \ -# [ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9} \ -# [ipx::get_bus_interfaces up_ch_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10))} \ -# [ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10} \ -# [ipx::get_bus_interfaces up_ch_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11))} \ -# [ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11} \ -# [ipx::get_bus_interfaces up_ch_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \ -# [ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12} \ -# [ipx::get_bus_interfaces up_ch_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \ -# [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13))} \ -# [ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13} \ -# [ipx::get_bus_interfaces up_ch_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14))} \ -# [ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14} \ -# [ipx::get_bus_interfaces up_ch_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ -# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15))} \ -# [ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15} \ -# [ipx::get_bus_interfaces up_ch_15 -of_objects [ipx::current_core]] -# adi_add_auto_fpga_spec_params -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:25:35 2021... diff --git a/adi_library/xilinx/axi_dacfifo/axi_dacfifo_ip.log b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_ip.log deleted file mode 100644 index d592269b..00000000 --- a/adi_library/xilinx/axi_dacfifo/axi_dacfifo_ip.log +++ /dev/null @@ -1,811 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_dacfifo_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_dacfifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_dacfifo [list \ -# "$ad_hdl_dir/library/common/ad_g2b.v" \ -# "$ad_hdl_dir/library/common/ad_b2g.v" \ -# "$ad_hdl_dir/library/common/ad_mem_asym.v" \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \ -# "$ad_hdl_dir/library/util_dacfifo/util_dacfifo_bypass.v" \ -# "axi_dacfifo_constr.xdc" \ -# "axi_dacfifo_wr.v" \ -# "axi_dacfifo_rd.v" \ -# "axi_dacfifo_address_buffer.v" \ -# "axi_dacfifo.v"] -# adi_ip_properties_lite axi_dacfifo -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_b2g.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_g2b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo/util_dacfifo_bypass.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_b2g.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_g2b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo/util_dacfifo_bypass.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '(DAC_DATA_WIDTH - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DAC_DATA_WIDTH - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DMA_DATA_WIDTH - 1):0' is present in all ports of the interface 'dma'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'. -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_rst'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_xfer_req' and definition port 'XFER_REQ'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'axi_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::infer_bus_interface {\ -# axi_awvalid \ -# axi_awid \ -# axi_awburst \ -# axi_awlock \ -# axi_awcache \ -# axi_awprot \ -# axi_awqos \ -# axi_awlen \ -# axi_awsize \ -# axi_awaddr \ -# axi_awready \ -# axi_wvalid \ -# axi_wdata \ -# axi_wstrb \ -# axi_wlast \ -# axi_wready \ -# axi_bvalid \ -# axi_bid \ -# axi_bresp \ -# axi_bready \ -# axi_arvalid \ -# axi_arid \ -# axi_arburst \ -# axi_arlock \ -# axi_arcache \ -# axi_arprot \ -# axi_arqos \ -# axi_arlen \ -# axi_arsize \ -# axi_araddr \ -# axi_arready \ -# axi_rvalid \ -# axi_rid \ -# axi_rresp \ -# axi_rlast \ -# axi_rdata \ -# axi_rready} \ -# xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -# ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'axi'. -# ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'. -# ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \ -# -of_objects [ipx::current_core]] -# set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ -# -of_objects [ipx::get_bus_interfaces axi_clk \ -# -of_objects [ipx::current_core]]] -# ipx::add_address_space axi [ipx::current_core] -# set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \ -# -of_objects [ipx::current_core]] -# set_property range 4294967296 [ipx::get_address_spaces axi \ -# -of_objects [ipx::current_core]] -# set_property width 512 [ipx::get_address_spaces axi \ -# -of_objects [ipx::current_core]] -# ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dma_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_rst'. -# ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:20:20 2021... diff --git a/adi_library/xilinx/axi_dacfifo/vivado.jou b/adi_library/xilinx/axi_dacfifo/vivado.jou deleted file mode 100644 index 63909688..00000000 --- a/adi_library/xilinx/axi_dacfifo/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:20:08 2021 -# Process ID: 8023 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo -# Command line: vivado -mode batch -source axi_dacfifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo/vivado.jou -#----------------------------------------------------------- -source axi_dacfifo_ip.tcl diff --git a/adi_library/xilinx/axi_dacfifo/vivado.log b/adi_library/xilinx/axi_dacfifo/vivado.log deleted file mode 100644 index 0b8223b8..00000000 --- a/adi_library/xilinx/axi_dacfifo/vivado.log +++ /dev/null @@ -1,816 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:20:08 2021 -# Process ID: 8023 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo -# Command line: vivado -mode batch -source axi_dacfifo_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo/vivado.jou -#----------------------------------------------------------- -source axi_dacfifo_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_dacfifo -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_dacfifo [list \ -# "$ad_hdl_dir/library/common/ad_g2b.v" \ -# "$ad_hdl_dir/library/common/ad_b2g.v" \ -# "$ad_hdl_dir/library/common/ad_mem_asym.v" \ -# "$ad_hdl_dir/library/common/ad_mem.v" \ -# "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \ -# "$ad_hdl_dir/library/util_dacfifo/util_dacfifo_bypass.v" \ -# "axi_dacfifo_constr.xdc" \ -# "axi_dacfifo_wr.v" \ -# "axi_dacfifo_rd.v" \ -# "axi_dacfifo_address_buffer.v" \ -# "axi_dacfifo.v"] -# adi_ip_properties_lite axi_dacfifo -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_b2g.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_g2b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo/util_dacfifo_bypass.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_b2g.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_g2b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo/util_dacfifo_bypass.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -WARNING: [IP_Flow 19-5150] The Range '(DAC_DATA_WIDTH - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DAC_DATA_WIDTH - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -WARNING: [IP_Flow 19-5150] The Range '(DMA_DATA_WIDTH - 1):0' is present in all ports of the interface 'dma'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'. -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -INFO: [IP_Flow 19-4728] Bus Interface 'dma_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_rst'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_xfer_req' and definition port 'XFER_REQ'. -WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_wdata' and definition port 'wdata'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_rdata' and definition port 'rdata'. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'axi_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'dma_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# ipx::infer_bus_interface {\ -# axi_awvalid \ -# axi_awid \ -# axi_awburst \ -# axi_awlock \ -# axi_awcache \ -# axi_awprot \ -# axi_awqos \ -# axi_awlen \ -# axi_awsize \ -# axi_awaddr \ -# axi_awready \ -# axi_wvalid \ -# axi_wdata \ -# axi_wstrb \ -# axi_wlast \ -# axi_wready \ -# axi_bvalid \ -# axi_bid \ -# axi_bresp \ -# axi_bready \ -# axi_arvalid \ -# axi_arid \ -# axi_arburst \ -# axi_arlock \ -# axi_arcache \ -# axi_arprot \ -# axi_arqos \ -# axi_arlen \ -# axi_arsize \ -# axi_araddr \ -# axi_arready \ -# axi_rvalid \ -# axi_rid \ -# axi_rresp \ -# axi_rlast \ -# axi_rdata \ -# axi_rready} \ -# xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -# ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'axi'. -# ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'. -# ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \ -# -of_objects [ipx::current_core]] -# set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ -# -of_objects [ipx::get_bus_interfaces axi_clk \ -# -of_objects [ipx::current_core]]] -# ipx::add_address_space axi [ipx::current_core] -# set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \ -# -of_objects [ipx::current_core]] -# set_property range 4294967296 [ipx::get_address_spaces axi \ -# -of_objects [ipx::current_core]] -# set_property width 512 [ipx::get_address_spaces axi \ -# -of_objects [ipx::current_core]] -# ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dma_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_rst'. -# ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'. -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:20:20 2021... diff --git a/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.log b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.log deleted file mode 100644 index 929d50d8..00000000 --- a/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.log +++ /dev/null @@ -1,1043 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source axi_xcvrlb_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_xcvrlb -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_xcvrlb [list \ -# "$ad_hdl_dir/library/xilinx/util_adxcvr/util_adxcvr_xch.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "axi_xcvrlb_constr.xdc" \ -# "axi_xcvrlb_1.v" \ -# "axi_xcvrlb.v" ] -# adi_ip_properties_lite axi_xcvrlb -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr/util_adxcvr_xch.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr/util_adxcvr_xch.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(NUM_OF_LANES - 1):0' is present in all ports of the interface 'interface_if_gt_tx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(NUM_OF_LANES - 1):0' is present in all ports of the interface 'interface_if_gt_rx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ref_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ref_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_init_bd_tcl -# adi_ip_bd axi_xcvrlb "bd/bd.tcl" -# ipx::remove_all_bus_interface [ipx::current_core] -# set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] -# ipx::infer_bus_interface {\ -# s_axi_awvalid \ -# s_axi_awaddr \ -# s_axi_awprot \ -# s_axi_awready \ -# s_axi_wvalid \ -# s_axi_wdata \ -# s_axi_wstrb \ -# s_axi_wready \ -# s_axi_bvalid \ -# s_axi_bresp \ -# s_axi_bready \ -# s_axi_arvalid \ -# s_axi_araddr \ -# s_axi_arprot \ -# s_axi_arready \ -# s_axi_rvalid \ -# s_axi_rdata \ -# s_axi_rresp \ -# s_axi_rready} \ -# xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -# ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -# ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ -# -of_objects [ipx::current_core]] -# set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ -# -of_objects [ipx::get_bus_interfaces s_axi_aclk \ -# -of_objects [ipx::current_core]]] -# ipx::add_memory_map {s_axi} [ipx::current_core] -# set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -# ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -# set_property range {1024} [ipx::get_address_blocks axi_lite \ -# -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -# adi_add_auto_fpga_spec_params -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:20:31 2021... diff --git a/adi_library/xilinx/axi_xcvrlb/vivado.jou b/adi_library/xilinx/axi_xcvrlb/vivado.jou deleted file mode 100644 index 25bf40b8..00000000 --- a/adi_library/xilinx/axi_xcvrlb/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:20:20 2021 -# Process ID: 8095 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb -# Command line: vivado -mode batch -source axi_xcvrlb_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb/vivado.jou -#----------------------------------------------------------- -source axi_xcvrlb_ip.tcl diff --git a/adi_library/xilinx/axi_xcvrlb/vivado.log b/adi_library/xilinx/axi_xcvrlb/vivado.log deleted file mode 100644 index 4e285ee4..00000000 --- a/adi_library/xilinx/axi_xcvrlb/vivado.log +++ /dev/null @@ -1,1048 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Dec 9 15:20:20 2021 -# Process ID: 8095 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb -# Command line: vivado -mode batch -source axi_xcvrlb_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb/vivado.jou -#----------------------------------------------------------- -source axi_xcvrlb_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create axi_xcvrlb -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files axi_xcvrlb [list \ -# "$ad_hdl_dir/library/xilinx/util_adxcvr/util_adxcvr_xch.v" \ -# "$ad_hdl_dir/library/common/up_xfer_status.v" \ -# "$ad_hdl_dir/library/common/ad_pnmon.v" \ -# "$ad_hdl_dir/library/common/up_axi.v" \ -# "axi_xcvrlb_constr.xdc" \ -# "axi_xcvrlb_1.v" \ -# "axi_xcvrlb.v" ] -# adi_ip_properties_lite axi_xcvrlb -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr/util_adxcvr_xch.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr/util_adxcvr_xch.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_xcvrlb'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5150] The Range '(NUM_OF_LANES - 1):0' is present in all ports of the interface 'interface_if_gt_tx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5150] The Range '(NUM_OF_LANES - 1):0' is present in all ports of the interface 'interface_if_gt_rx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array. -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 'ref_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3153] Bus Interface 'ref_clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_init_bd_tcl -# adi_ip_bd axi_xcvrlb "bd/bd.tcl" -# ipx::remove_all_bus_interface [ipx::current_core] -# set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] -# ipx::infer_bus_interface {\ -# s_axi_awvalid \ -# s_axi_awaddr \ -# s_axi_awprot \ -# s_axi_awready \ -# s_axi_wvalid \ -# s_axi_wdata \ -# s_axi_wstrb \ -# s_axi_wready \ -# s_axi_bvalid \ -# s_axi_bresp \ -# s_axi_bready \ -# s_axi_arvalid \ -# s_axi_araddr \ -# s_axi_arprot \ -# s_axi_arready \ -# s_axi_rvalid \ -# s_axi_rdata \ -# s_axi_rresp \ -# s_axi_rready} \ -# xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument). -# ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. -# ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument). -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. -# ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ -# -of_objects [ipx::current_core]] -# set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ -# -of_objects [ipx::get_bus_interfaces s_axi_aclk \ -# -of_objects [ipx::current_core]]] -# ipx::add_memory_map {s_axi} [ipx::current_core] -# set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -# ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -# set_property range {1024} [ipx::get_address_blocks axi_lite \ -# -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -# adi_add_auto_fpga_spec_params -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:20:31 2021... diff --git a/adi_library/xilinx/util_adxcvr/util_adxcvr_ip.log b/adi_library/xilinx/util_adxcvr/util_adxcvr_ip.log deleted file mode 100644 index d34119dd..00000000 --- a/adi_library/xilinx/util_adxcvr/util_adxcvr_ip.log +++ /dev/null @@ -1,4698 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_adxcvr_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_adxcvr -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_adxcvr [list \ -# "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \ -# "util_adxcvr_constr.xdc" \ -# "util_adxcvr_xcm.v" \ -# "util_adxcvr_xch.v" \ -# "util_adxcvr.v" \ -# "bd/bd.tcl" ] -# adi_ip_properties_lite util_adxcvr -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-4821] For module 'util_adxcvr', parameter 'RX_XMODE_SEL' is inferred to be bitString format. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_12_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_12_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_12_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_12_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [Common 17-14] Message 'IP_Flow 19-5151' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-4728] Bus Interface 'up_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'up_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rstn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_0': A port map to the required logical port "qpll_ref_clk" of the bus abstraction "analog.com:interface:if_gt_qpll_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_12': A port map to the required logical port "qpll_ref_clk" of the bus abstraction "analog.com:interface:if_gt_qpll_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_4': A port map to the required logical port "qpll_ref_clk" of the bus abstraction "analog.com:interface:if_gt_qpll_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_8': A port map to the required logical port "qpll_ref_clk" of the bus abstraction "analog.com:interface:if_gt_qpll_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3157] Bus Interface 'up_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'up_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'up_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Synthesis'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Synthesis'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Simulation'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Simulation'. -Resolution: Remove the file from the specified file group. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_bd util_adxcvr "bd/bd.tcl" -# ipx::remove_all_bus_interface [ipx::current_core] -# ipx::infer_bus_interface up_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface qpll_ref_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface qpll_ref_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface qpll_ref_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface qpll_ref_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'up_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'up_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rstn'. -# ipx::infer_bus_interface up_rx_rst_0 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_0': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_0'. -# ipx::infer_bus_interface up_rx_rst_1 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_1': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_1'. -# ipx::infer_bus_interface up_rx_rst_2 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_2': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_2'. -# ipx::infer_bus_interface up_rx_rst_3 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_3': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_3'. -# ipx::infer_bus_interface up_rx_rst_4 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_4': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_4'. -# ipx::infer_bus_interface up_rx_rst_5 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_5': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_5'. -# ipx::infer_bus_interface up_rx_rst_6 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_6': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_6'. -# ipx::infer_bus_interface up_rx_rst_7 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_7': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_7'. -# ipx::infer_bus_interface up_rx_rst_8 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_8': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_8'. -# ipx::infer_bus_interface up_rx_rst_9 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_9': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_9'. -# ipx::infer_bus_interface up_rx_rst_10 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_10': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_10'. -# ipx::infer_bus_interface up_rx_rst_11 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_11': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_11'. -# ipx::infer_bus_interface up_rx_rst_12 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_12': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_12'. -# ipx::infer_bus_interface up_rx_rst_13 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_13': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_13'. -# ipx::infer_bus_interface up_rx_rst_14 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_14': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_14'. -# ipx::infer_bus_interface up_rx_rst_15 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_15': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_15'. -# ipx::infer_bus_interface up_tx_rst_0 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_1 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_2 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_3 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_4 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_5 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_6 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_7 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_8 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_9 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_10 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_11 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_12 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_13 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_14 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_15 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] -# for {set n 0} {$n < 16} {incr n} { -# -# if {($n%4) == 0} { -# adi_if_infer_bus analog.com:interface:if_xcvr_cm slave up_cm_${n} [list \ -# "enb up_cm_enb_${n} "\ -# "addr up_cm_addr_${n} "\ -# "wr up_cm_wr_${n} "\ -# "wdata up_cm_wdata_${n} "\ -# "rdata up_cm_rdata_${n} "\ -# "ready up_cm_ready_${n} "] -# } -# -# adi_if_infer_bus analog.com:interface:if_xcvr_cm slave up_es_${n} [list \ -# "enb up_es_enb_${n} "\ -# "addr up_es_addr_${n} "\ -# "wr up_es_wr_${n} "\ -# "wdata up_es_wdata_${n} "\ -# "rdata up_es_rdata_${n} "\ -# "reset up_es_reset_${n} "\ -# "ready up_es_ready_${n} "] -# -# adi_if_infer_bus analog.com:interface:if_xcvr_ch slave up_rx_${n} [list \ -# "pll_locked up_rx_pll_locked_${n} "\ -# "rst up_rx_rst_${n} "\ -# "user_ready up_rx_user_ready_${n} "\ -# "rst_done up_rx_rst_done_${n} "\ -# "lpm_dfe_n up_rx_lpm_dfe_n_${n} "\ -# "rate up_rx_rate_${n} "\ -# "sys_clk_sel up_rx_sys_clk_sel_${n} "\ -# "out_clk_sel up_rx_out_clk_sel_${n} "\ -# "enb up_rx_enb_${n} "\ -# "addr up_rx_addr_${n} "\ -# "wr up_rx_wr_${n} "\ -# "wdata up_rx_wdata_${n} "\ -# "rdata up_rx_rdata_${n} "\ -# "ready up_rx_ready_${n} "] -# -# adi_if_infer_bus analog.com:interface:if_xcvr_ch slave up_tx_${n} [list \ -# "pll_locked up_tx_pll_locked_${n} "\ -# "rst up_tx_rst_${n} "\ -# "user_ready up_tx_user_ready_${n} "\ -# "rst_done up_tx_rst_done_${n} "\ -# "lpm_dfe_n up_tx_lpm_dfe_n_${n} "\ -# "rate up_tx_rate_${n} "\ -# "sys_clk_sel up_tx_sys_clk_sel_${n} "\ -# "out_clk_sel up_tx_out_clk_sel_${n} "\ -# "tx_diffctrl up_tx_diffctrl_${n} "\ -# "tx_postcursor up_tx_postcursor_${n} "\ -# "tx_precursor up_tx_precursor_${n} "\ -# "enb up_tx_enb_${n} "\ -# "addr up_tx_addr_${n} "\ -# "wr up_tx_wr_${n} "\ -# "wdata up_tx_wdata_${n} "\ -# "rdata up_tx_rdata_${n} "\ -# "ready up_tx_ready_${n} "] -# -# ipx::add_bus_interface rx_${n} [ipx::current_core] -# set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 \ -# [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] -# set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus:1.0 \ -# [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] -# set_property interface_mode master [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] -# ipx::add_port_map rxcharisk [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] -# set_property physical_name rx_charisk_${n} [ipx::get_port_maps rxcharisk -of_objects \ -# [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] -# ipx::add_port_map rxnotintable [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] -# set_property physical_name rx_notintable_${n} [ipx::get_port_maps rxnotintable -of_objects \ -# [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] -# ipx::add_port_map rxdisperr [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] -# set_property physical_name rx_disperr_${n} [ipx::get_port_maps rxdisperr -of_objects \ -# [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] -# ipx::add_port_map rxdata [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] -# set_property physical_name rx_data_${n} [ipx::get_port_maps rxdata -of_objects \ -# [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] -# -# ipx::add_bus_interface tx_${n} [ipx::current_core] -# set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 \ -# [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] -# set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus:1.0 \ -# [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] -# set_property interface_mode slave [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] -# ipx::add_port_map txcharisk [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] -# set_property physical_name tx_charisk_${n} [ipx::get_port_maps txcharisk -of_objects \ -# [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]] -# ipx::add_port_map txdata [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] -# set_property physical_name tx_data_${n} [ipx::get_port_maps txdata -of_objects \ -# [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]] -# -# } -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ -# [ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ -# [ipx::get_bus_interfaces up_rx_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ -# [ipx::get_bus_interfaces rx_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ -# [ipx::get_ports rx_*0* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ -# [ipx::get_ports up_rx_rst_0 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ -# [ipx::get_bus_interfaces up_tx_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ -# [ipx::get_bus_interfaces tx_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ -# [ipx::get_ports tx_*0* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ -# [ipx::get_ports up_tx_rst_0 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)} \ -# [ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \ -# [ipx::get_ports qpll_ref_clk_0 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_qpll_rst_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \ -# [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ -# [ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ -# [ipx::get_bus_interfaces up_rx_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ -# [ipx::get_bus_interfaces rx_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ -# [ipx::get_ports rx_*1* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ -# [ipx::get_ports up_rx_rst_1 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ -# [ipx::get_bus_interfaces up_tx_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ -# [ipx::get_bus_interfaces tx_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ -# [ipx::get_ports tx_*1* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ -# [ipx::get_ports up_tx_rst_1 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1)} \ -# [ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ -# [ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ -# [ipx::get_bus_interfaces up_rx_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ -# [ipx::get_bus_interfaces rx_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ -# [ipx::get_ports rx_*2* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ -# [ipx::get_ports up_rx_rst_2 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ -# [ipx::get_bus_interfaces up_tx_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ -# [ipx::get_bus_interfaces tx_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ -# [ipx::get_ports tx_*2* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ -# [ipx::get_ports up_tx_rst_2 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2)} \ -# [ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ -# [ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ -# [ipx::get_bus_interfaces up_rx_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ -# [ipx::get_bus_interfaces rx_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ -# [ipx::get_ports rx_*3* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ -# [ipx::get_ports up_rx_rst_3 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ -# [ipx::get_bus_interfaces up_tx_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ -# [ipx::get_bus_interfaces tx_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ -# [ipx::get_ports tx_*3* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ -# [ipx::get_ports up_tx_rst_3 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3)} \ -# [ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ -# [ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ -# [ipx::get_bus_interfaces up_rx_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ -# [ipx::get_bus_interfaces rx_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ -# [ipx::get_ports rx_*4* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ -# [ipx::get_ports up_rx_rst_4 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ -# [ipx::get_bus_interfaces up_tx_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ -# [ipx::get_bus_interfaces tx_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ -# [ipx::get_ports tx_*4* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ -# [ipx::get_ports up_tx_rst_4 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)} \ -# [ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \ -# [ipx::get_ports qpll_ref_clk_4 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_qpll_rst_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \ -# [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ -# [ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ -# [ipx::get_bus_interfaces up_rx_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ -# [ipx::get_bus_interfaces rx_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ -# [ipx::get_ports rx_*5* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ -# [ipx::get_ports up_rx_rst_5 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ -# [ipx::get_bus_interfaces up_tx_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ -# [ipx::get_bus_interfaces tx_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ -# [ipx::get_ports tx_*5* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ -# [ipx::get_ports up_tx_rst_5 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5)} \ -# [ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ -# [ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ -# [ipx::get_bus_interfaces up_rx_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ -# [ipx::get_bus_interfaces rx_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ -# [ipx::get_ports rx_*6* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ -# [ipx::get_ports up_rx_rst_6 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ -# [ipx::get_bus_interfaces up_tx_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ -# [ipx::get_bus_interfaces tx_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ -# [ipx::get_ports tx_*6* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ -# [ipx::get_ports up_tx_rst_6 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6)} \ -# [ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ -# [ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ -# [ipx::get_bus_interfaces up_rx_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ -# [ipx::get_bus_interfaces rx_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ -# [ipx::get_ports rx_*7* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ -# [ipx::get_ports up_rx_rst_7 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ -# [ipx::get_bus_interfaces up_tx_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ -# [ipx::get_bus_interfaces tx_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ -# [ipx::get_ports tx_*7* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ -# [ipx::get_ports up_tx_rst_7 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7)} \ -# [ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ -# [ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ -# [ipx::get_bus_interfaces up_rx_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ -# [ipx::get_bus_interfaces rx_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ -# [ipx::get_ports rx_*8* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ -# [ipx::get_ports up_rx_rst_8 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ -# [ipx::get_bus_interfaces up_tx_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ -# [ipx::get_bus_interfaces tx_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ -# [ipx::get_ports tx_*8* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ -# [ipx::get_ports up_tx_rst_8 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)} \ -# [ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \ -# [ipx::get_ports qpll_ref_clk_8 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_qpll_rst_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \ -# [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ -# [ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ -# [ipx::get_bus_interfaces up_rx_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ -# [ipx::get_bus_interfaces rx_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ -# [ipx::get_ports rx_*9* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ -# [ipx::get_ports up_rx_rst_9 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ -# [ipx::get_bus_interfaces up_tx_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ -# [ipx::get_bus_interfaces tx_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ -# [ipx::get_ports tx_*9* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ -# [ipx::get_ports up_tx_rst_9 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9)} \ -# [ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ -# [ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ -# [ipx::get_bus_interfaces up_rx_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ -# [ipx::get_bus_interfaces rx_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ -# [ipx::get_ports rx_*10* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ -# [ipx::get_ports up_rx_rst_10 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ -# [ipx::get_bus_interfaces up_tx_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ -# [ipx::get_bus_interfaces tx_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ -# [ipx::get_ports tx_*10* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ -# [ipx::get_ports up_tx_rst_10 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10)} \ -# [ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ -# [ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ -# [ipx::get_bus_interfaces up_rx_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ -# [ipx::get_bus_interfaces rx_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ -# [ipx::get_ports rx_*11* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ -# [ipx::get_ports up_rx_rst_11 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ -# [ipx::get_bus_interfaces up_tx_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ -# [ipx::get_bus_interfaces tx_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ -# [ipx::get_ports tx_*11* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ -# [ipx::get_ports up_tx_rst_11 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11)} \ -# [ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ -# [ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ -# [ipx::get_bus_interfaces up_rx_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ -# [ipx::get_bus_interfaces rx_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ -# [ipx::get_ports rx_*12* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ -# [ipx::get_ports up_rx_rst_12 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ -# [ipx::get_bus_interfaces up_tx_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ -# [ipx::get_bus_interfaces tx_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ -# [ipx::get_ports tx_*12* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ -# [ipx::get_ports up_tx_rst_12 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)} \ -# [ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \ -# [ipx::get_ports qpll_ref_clk_12 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_qpll_rst_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \ -# [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ -# [ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ -# [ipx::get_bus_interfaces up_rx_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ -# [ipx::get_bus_interfaces rx_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ -# [ipx::get_ports rx_*13* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ -# [ipx::get_ports up_rx_rst_13 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ -# [ipx::get_bus_interfaces up_tx_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ -# [ipx::get_bus_interfaces tx_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ -# [ipx::get_ports tx_*13* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ -# [ipx::get_ports up_tx_rst_13 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13)} \ -# [ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ -# [ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ -# [ipx::get_bus_interfaces up_rx_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ -# [ipx::get_bus_interfaces rx_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ -# [ipx::get_ports rx_*14* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ -# [ipx::get_ports up_rx_rst_14 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ -# [ipx::get_bus_interfaces up_tx_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ -# [ipx::get_bus_interfaces tx_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ -# [ipx::get_ports tx_*14* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ -# [ipx::get_ports up_tx_rst_14 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14)} \ -# [ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ -# [ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ -# [ipx::get_bus_interfaces up_rx_15 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ -# [ipx::get_bus_interfaces rx_15 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ -# [ipx::get_ports rx_*15* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ -# [ipx::get_ports up_rx_rst_15 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ -# [ipx::get_bus_interfaces up_tx_15 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ -# [ipx::get_bus_interfaces tx_15 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ -# [ipx::get_ports tx_*15* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ -# [ipx::get_ports up_tx_rst_15 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15)} \ -# [ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_15 -of_objects [ipx::current_core]] -# adi_add_auto_fpga_spec_params -# set cc [ipx::current_core] -# set param [ipx::get_user_parameters CH_HSPMUX -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2424 : \ -# {$XCVR_TYPE == 9} ? 0x2020 : 0x0]]} \ -# ] $param -# set param [ipx::get_user_parameters PPF0_CFG -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x800 : 0x600]]} \ -# ] $param -# set param [ipx::get_user_parameters RXPI_CFG0 -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2 : \ -# {$XCVR_TYPE == 9} ? 0x100 : 0x0]]} \ -# ] $param -# set param [ipx::get_user_parameters RXPI_CFG1 -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x15 : 0x0]]} \ -# ] $param -# set param [ipx::get_user_parameters RTX_BUF_CML_CTRL -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x3 : 0x0]]} \ -# ] $param -# set param [ipx::get_user_parameters QPLL_LPF -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x37f : 0x137]]} \ -# ] $param -# set param [ipx::get_user_parameters RXCDR_CFG3_GEN2 -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x1a ]]} \ -# ] $param -# set param [ipx::get_user_parameters RXCDR_CFG3_GEN4 -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x24 ]]} \ -# ] $param -# set param [ipx::get_user_parameters TX_PI_BIASSET -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {expr {$XCVR_TYPE == 9} ? 0 : 1} \ -# ] $param -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:25:46 2021... diff --git a/adi_library/xilinx/util_adxcvr/vivado.jou b/adi_library/xilinx/util_adxcvr/vivado.jou deleted file mode 100644 index 27eb03c6..00000000 --- a/adi_library/xilinx/util_adxcvr/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:25:36 2021 -# Process ID: 146223 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr -# Command line: vivado -mode batch -source util_adxcvr_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr/vivado.jou -#----------------------------------------------------------- -source util_adxcvr_ip.tcl diff --git a/adi_library/xilinx/util_adxcvr/vivado.log b/adi_library/xilinx/util_adxcvr/vivado.log deleted file mode 100644 index 2d7640b5..00000000 --- a/adi_library/xilinx/util_adxcvr/vivado.log +++ /dev/null @@ -1,4703 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 20:25:36 2021 -# Process ID: 146223 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr -# Command line: vivado -mode batch -source util_adxcvr_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr/vivado.jou -#----------------------------------------------------------- -source util_adxcvr_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_adxcvr -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_adxcvr [list \ -# "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \ -# "util_adxcvr_constr.xdc" \ -# "util_adxcvr_xcm.v" \ -# "util_adxcvr_xch.v" \ -# "util_adxcvr.v" \ -# "bd/bd.tcl" ] -# adi_ip_properties_lite util_adxcvr -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. -INFO: [IP_Flow 19-4821] For module 'util_adxcvr', parameter 'RX_XMODE_SEL' is inferred to be bitString format. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_10_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_16' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_17' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_18' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_19' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_20' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_21' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_22' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_23' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_24' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_25' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_26' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_27' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_28' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_29' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_30' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_31' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_11_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_12_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_12_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_12_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master. -INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference. -INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_12_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories). -INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave. -INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'rx_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'tx_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '4:0' is present in all ports of the interface 'up_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [IP_Flow 19-5151] The Range '2:0' is present in all ports of the interface 'up_sel_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'. -INFO: [Common 17-14] Message 'IP_Flow 19-5151' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [IP_Flow 19-4728] Bus Interface 'up_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'up_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rstn'. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_0' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_10' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_10_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_11' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_11_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_12' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_12_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_13' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_13_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_14' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_14_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_15' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_15_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_1' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_2' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_2_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_3' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_3_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_4' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_4_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_5' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_5_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_6' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_6_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_7' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_7_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_8' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_8_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_9' and definition port 'DATA'. -WARNING: [IP_Flow 19-1965] Bus Interface 'rx_9_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_10_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_11_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_12_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_13_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_14_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_15_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_2_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_3_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_4_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_5_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_6_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_7_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_8_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_16': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_17': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_18': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_19': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_20': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_21': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_22': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_23': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_24': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_25': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_26': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_27': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_28': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_29': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_30': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_31': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'tx_9_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_0': A port map to the required logical port "qpll_ref_clk" of the bus abstraction "analog.com:interface:if_gt_qpll_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_12': A port map to the required logical port "qpll_ref_clk" of the bus abstraction "analog.com:interface:if_gt_qpll_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_4': A port map to the required logical port "qpll_ref_clk" of the bus abstraction "analog.com:interface:if_gt_qpll_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_8': A port map to the required logical port "qpll_ref_clk" of the bus abstraction "analog.com:interface:if_gt_qpll_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_10_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_11_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_13_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_14_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_15_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_1_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_2_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_3_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_5_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_6_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_7_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_rx_9_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_10_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_11_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_13_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_14_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_15_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_1_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_2_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_3_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_5_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_6_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_7_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-1965] Bus Interface 'up_tx_9_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing. -WARNING: [IP_Flow 19-3157] Bus Interface 'up_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'up_rstn' is not *resetn - please double check the POLARITY setting. -WARNING: [IP_Flow 19-3153] Bus Interface 'up_clk': ASSOCIATED_BUSIF bus parameter is missing. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Synthesis'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Synthesis'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Simulation'. -Resolution: Remove the file from the specified file group. -WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Simulation'. -Resolution: Remove the file from the specified file group. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_bd util_adxcvr "bd/bd.tcl" -# ipx::remove_all_bus_interface [ipx::current_core] -# ipx::infer_bus_interface up_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface cpll_ref_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface qpll_ref_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface qpll_ref_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface qpll_ref_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface qpll_ref_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_out_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_out_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface rx_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface tx_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'up_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. -INFO: [IP_Flow 19-4728] Bus Interface 'up_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rstn'. -# ipx::infer_bus_interface up_rx_rst_0 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_0': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_0'. -# ipx::infer_bus_interface up_rx_rst_1 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_1': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_1'. -# ipx::infer_bus_interface up_rx_rst_2 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_2': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_2'. -# ipx::infer_bus_interface up_rx_rst_3 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_3': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_3'. -# ipx::infer_bus_interface up_rx_rst_4 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_4': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_4'. -# ipx::infer_bus_interface up_rx_rst_5 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_5': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_5'. -# ipx::infer_bus_interface up_rx_rst_6 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_6': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_6'. -# ipx::infer_bus_interface up_rx_rst_7 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_7': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_7'. -# ipx::infer_bus_interface up_rx_rst_8 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_8': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_8'. -# ipx::infer_bus_interface up_rx_rst_9 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_9': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_9'. -# ipx::infer_bus_interface up_rx_rst_10 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_10': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_10'. -# ipx::infer_bus_interface up_rx_rst_11 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_11': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_11'. -# ipx::infer_bus_interface up_rx_rst_12 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_12': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_12'. -# ipx::infer_bus_interface up_rx_rst_13 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_13': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_13'. -# ipx::infer_bus_interface up_rx_rst_14 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_14': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_14'. -# ipx::infer_bus_interface up_rx_rst_15 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-4728] Bus Interface 'cpll_ref_clk_15': Added interface parameter 'ASSOCIATED_RESET' with value 'up_rx_rst_15'. -# ipx::infer_bus_interface up_tx_rst_0 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_1 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_2 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_3 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_4 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_5 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_6 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_7 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_8 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_9 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_10 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_11 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_12 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_13 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_14 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# ipx::infer_bus_interface up_tx_rst_15 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -# set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] -# for {set n 0} {$n < 16} {incr n} { -# -# if {($n%4) == 0} { -# adi_if_infer_bus analog.com:interface:if_xcvr_cm slave up_cm_${n} [list \ -# "enb up_cm_enb_${n} "\ -# "addr up_cm_addr_${n} "\ -# "wr up_cm_wr_${n} "\ -# "wdata up_cm_wdata_${n} "\ -# "rdata up_cm_rdata_${n} "\ -# "ready up_cm_ready_${n} "] -# } -# -# adi_if_infer_bus analog.com:interface:if_xcvr_cm slave up_es_${n} [list \ -# "enb up_es_enb_${n} "\ -# "addr up_es_addr_${n} "\ -# "wr up_es_wr_${n} "\ -# "wdata up_es_wdata_${n} "\ -# "rdata up_es_rdata_${n} "\ -# "reset up_es_reset_${n} "\ -# "ready up_es_ready_${n} "] -# -# adi_if_infer_bus analog.com:interface:if_xcvr_ch slave up_rx_${n} [list \ -# "pll_locked up_rx_pll_locked_${n} "\ -# "rst up_rx_rst_${n} "\ -# "user_ready up_rx_user_ready_${n} "\ -# "rst_done up_rx_rst_done_${n} "\ -# "lpm_dfe_n up_rx_lpm_dfe_n_${n} "\ -# "rate up_rx_rate_${n} "\ -# "sys_clk_sel up_rx_sys_clk_sel_${n} "\ -# "out_clk_sel up_rx_out_clk_sel_${n} "\ -# "enb up_rx_enb_${n} "\ -# "addr up_rx_addr_${n} "\ -# "wr up_rx_wr_${n} "\ -# "wdata up_rx_wdata_${n} "\ -# "rdata up_rx_rdata_${n} "\ -# "ready up_rx_ready_${n} "] -# -# adi_if_infer_bus analog.com:interface:if_xcvr_ch slave up_tx_${n} [list \ -# "pll_locked up_tx_pll_locked_${n} "\ -# "rst up_tx_rst_${n} "\ -# "user_ready up_tx_user_ready_${n} "\ -# "rst_done up_tx_rst_done_${n} "\ -# "lpm_dfe_n up_tx_lpm_dfe_n_${n} "\ -# "rate up_tx_rate_${n} "\ -# "sys_clk_sel up_tx_sys_clk_sel_${n} "\ -# "out_clk_sel up_tx_out_clk_sel_${n} "\ -# "tx_diffctrl up_tx_diffctrl_${n} "\ -# "tx_postcursor up_tx_postcursor_${n} "\ -# "tx_precursor up_tx_precursor_${n} "\ -# "enb up_tx_enb_${n} "\ -# "addr up_tx_addr_${n} "\ -# "wr up_tx_wr_${n} "\ -# "wdata up_tx_wdata_${n} "\ -# "rdata up_tx_rdata_${n} "\ -# "ready up_tx_ready_${n} "] -# -# ipx::add_bus_interface rx_${n} [ipx::current_core] -# set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 \ -# [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] -# set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus:1.0 \ -# [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] -# set_property interface_mode master [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] -# ipx::add_port_map rxcharisk [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] -# set_property physical_name rx_charisk_${n} [ipx::get_port_maps rxcharisk -of_objects \ -# [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] -# ipx::add_port_map rxnotintable [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] -# set_property physical_name rx_notintable_${n} [ipx::get_port_maps rxnotintable -of_objects \ -# [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] -# ipx::add_port_map rxdisperr [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] -# set_property physical_name rx_disperr_${n} [ipx::get_port_maps rxdisperr -of_objects \ -# [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] -# ipx::add_port_map rxdata [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] -# set_property physical_name rx_data_${n} [ipx::get_port_maps rxdata -of_objects \ -# [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] -# -# ipx::add_bus_interface tx_${n} [ipx::current_core] -# set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 \ -# [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] -# set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus:1.0 \ -# [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] -# set_property interface_mode slave [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] -# ipx::add_port_map txcharisk [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] -# set_property physical_name tx_charisk_${n} [ipx::get_port_maps txcharisk -of_objects \ -# [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]] -# ipx::add_port_map txdata [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] -# set_property physical_name tx_data_${n} [ipx::get_port_maps txdata -of_objects \ -# [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]] -# -# } -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ -# [ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ -# [ipx::get_bus_interfaces up_rx_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ -# [ipx::get_bus_interfaces rx_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ -# [ipx::get_ports rx_*0* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ -# [ipx::get_ports up_rx_rst_0 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ -# [ipx::get_bus_interfaces up_tx_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ -# [ipx::get_bus_interfaces tx_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ -# [ipx::get_ports tx_*0* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ -# [ipx::get_ports up_tx_rst_0 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)} \ -# [ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \ -# [ipx::get_ports qpll_ref_clk_0 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_qpll_rst_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \ -# [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ -# [ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ -# [ipx::get_bus_interfaces up_rx_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ -# [ipx::get_bus_interfaces rx_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ -# [ipx::get_ports rx_*1* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ -# [ipx::get_ports up_rx_rst_1 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ -# [ipx::get_bus_interfaces up_tx_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ -# [ipx::get_bus_interfaces tx_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ -# [ipx::get_ports tx_*1* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ -# [ipx::get_ports up_tx_rst_1 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1)} \ -# [ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_1 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ -# [ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ -# [ipx::get_bus_interfaces up_rx_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ -# [ipx::get_bus_interfaces rx_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ -# [ipx::get_ports rx_*2* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ -# [ipx::get_ports up_rx_rst_2 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ -# [ipx::get_bus_interfaces up_tx_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ -# [ipx::get_bus_interfaces tx_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ -# [ipx::get_ports tx_*2* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ -# [ipx::get_ports up_tx_rst_2 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2)} \ -# [ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_2 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ -# [ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ -# [ipx::get_bus_interfaces up_rx_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ -# [ipx::get_bus_interfaces rx_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ -# [ipx::get_ports rx_*3* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ -# [ipx::get_ports up_rx_rst_3 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ -# [ipx::get_bus_interfaces up_tx_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ -# [ipx::get_bus_interfaces tx_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ -# [ipx::get_ports tx_*3* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ -# [ipx::get_ports up_tx_rst_3 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3)} \ -# [ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_3 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ -# [ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ -# [ipx::get_bus_interfaces up_rx_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ -# [ipx::get_bus_interfaces rx_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ -# [ipx::get_ports rx_*4* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ -# [ipx::get_ports up_rx_rst_4 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ -# [ipx::get_bus_interfaces up_tx_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ -# [ipx::get_bus_interfaces tx_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ -# [ipx::get_ports tx_*4* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ -# [ipx::get_ports up_tx_rst_4 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)} \ -# [ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \ -# [ipx::get_ports qpll_ref_clk_4 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_qpll_rst_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \ -# [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ -# [ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ -# [ipx::get_bus_interfaces up_rx_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ -# [ipx::get_bus_interfaces rx_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ -# [ipx::get_ports rx_*5* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ -# [ipx::get_ports up_rx_rst_5 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ -# [ipx::get_bus_interfaces up_tx_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ -# [ipx::get_bus_interfaces tx_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ -# [ipx::get_ports tx_*5* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ -# [ipx::get_ports up_tx_rst_5 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5)} \ -# [ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_5 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ -# [ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ -# [ipx::get_bus_interfaces up_rx_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ -# [ipx::get_bus_interfaces rx_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ -# [ipx::get_ports rx_*6* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ -# [ipx::get_ports up_rx_rst_6 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ -# [ipx::get_bus_interfaces up_tx_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ -# [ipx::get_bus_interfaces tx_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ -# [ipx::get_ports tx_*6* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ -# [ipx::get_ports up_tx_rst_6 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6)} \ -# [ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_6 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ -# [ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ -# [ipx::get_bus_interfaces up_rx_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ -# [ipx::get_bus_interfaces rx_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ -# [ipx::get_ports rx_*7* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ -# [ipx::get_ports up_rx_rst_7 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ -# [ipx::get_bus_interfaces up_tx_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ -# [ipx::get_bus_interfaces tx_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ -# [ipx::get_ports tx_*7* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ -# [ipx::get_ports up_tx_rst_7 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7)} \ -# [ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_7 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ -# [ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ -# [ipx::get_bus_interfaces up_rx_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ -# [ipx::get_bus_interfaces rx_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ -# [ipx::get_ports rx_*8* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ -# [ipx::get_ports up_rx_rst_8 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ -# [ipx::get_bus_interfaces up_tx_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ -# [ipx::get_bus_interfaces tx_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ -# [ipx::get_ports tx_*8* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ -# [ipx::get_ports up_tx_rst_8 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)} \ -# [ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \ -# [ipx::get_ports qpll_ref_clk_8 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_qpll_rst_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \ -# [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ -# [ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ -# [ipx::get_bus_interfaces up_rx_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ -# [ipx::get_bus_interfaces rx_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ -# [ipx::get_ports rx_*9* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ -# [ipx::get_ports up_rx_rst_9 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ -# [ipx::get_bus_interfaces up_tx_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ -# [ipx::get_bus_interfaces tx_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ -# [ipx::get_ports tx_*9* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ -# [ipx::get_ports up_tx_rst_9 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9)} \ -# [ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_9 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ -# [ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ -# [ipx::get_bus_interfaces up_rx_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ -# [ipx::get_bus_interfaces rx_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ -# [ipx::get_ports rx_*10* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ -# [ipx::get_ports up_rx_rst_10 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ -# [ipx::get_bus_interfaces up_tx_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ -# [ipx::get_bus_interfaces tx_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ -# [ipx::get_ports tx_*10* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ -# [ipx::get_ports up_tx_rst_10 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10)} \ -# [ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_10 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ -# [ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ -# [ipx::get_bus_interfaces up_rx_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ -# [ipx::get_bus_interfaces rx_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ -# [ipx::get_ports rx_*11* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ -# [ipx::get_ports up_rx_rst_11 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ -# [ipx::get_bus_interfaces up_tx_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ -# [ipx::get_bus_interfaces tx_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ -# [ipx::get_ports tx_*11* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ -# [ipx::get_ports up_tx_rst_11 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11)} \ -# [ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_11 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ -# [ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ -# [ipx::get_bus_interfaces up_rx_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ -# [ipx::get_bus_interfaces rx_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ -# [ipx::get_ports rx_*12* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ -# [ipx::get_ports up_rx_rst_12 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ -# [ipx::get_bus_interfaces up_tx_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ -# [ipx::get_bus_interfaces tx_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ -# [ipx::get_ports tx_*12* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ -# [ipx::get_ports up_tx_rst_12 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)} \ -# [ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \ -# [ipx::get_ports qpll_ref_clk_12 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_qpll_rst_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \ -# (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \ -# [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ -# [ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ -# [ipx::get_bus_interfaces up_rx_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ -# [ipx::get_bus_interfaces rx_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ -# [ipx::get_ports rx_*13* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ -# [ipx::get_ports up_rx_rst_13 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ -# [ipx::get_bus_interfaces up_tx_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ -# [ipx::get_bus_interfaces tx_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ -# [ipx::get_ports tx_*13* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ -# [ipx::get_ports up_tx_rst_13 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13)} \ -# [ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_13 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ -# [ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ -# [ipx::get_bus_interfaces up_rx_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ -# [ipx::get_bus_interfaces rx_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ -# [ipx::get_ports rx_*14* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ -# [ipx::get_ports up_rx_rst_14 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ -# [ipx::get_bus_interfaces up_tx_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ -# [ipx::get_bus_interfaces tx_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ -# [ipx::get_ports tx_*14* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ -# [ipx::get_ports up_tx_rst_14 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14)} \ -# [ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_14 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ -# [ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ -# [ipx::get_bus_interfaces up_rx_15 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ -# [ipx::get_bus_interfaces rx_15 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ -# [ipx::get_ports rx_*15* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ -# [ipx::get_ports up_rx_rst_15 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ -# [ipx::get_bus_interfaces up_tx_15 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ -# [ipx::get_bus_interfaces tx_15 -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ -# [ipx::get_ports tx_*15* -of_objects [ipx::current_core]] -# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ -# [ipx::get_ports up_tx_rst_15 -of_objects [ipx::current_core]] \ -# -# set_property enablement_dependency \ -# {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15) or \ -# (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15)} \ -# [ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]] \ -# [ipx::get_ports up_cpll_rst_15 -of_objects [ipx::current_core]] -# adi_add_auto_fpga_spec_params -# set cc [ipx::current_core] -# set param [ipx::get_user_parameters CH_HSPMUX -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2424 : \ -# {$XCVR_TYPE == 9} ? 0x2020 : 0x0]]} \ -# ] $param -# set param [ipx::get_user_parameters PPF0_CFG -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x800 : 0x600]]} \ -# ] $param -# set param [ipx::get_user_parameters RXPI_CFG0 -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2 : \ -# {$XCVR_TYPE == 9} ? 0x100 : 0x0]]} \ -# ] $param -# set param [ipx::get_user_parameters RXPI_CFG1 -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x15 : 0x0]]} \ -# ] $param -# set param [ipx::get_user_parameters RTX_BUF_CML_CTRL -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x3 : 0x0]]} \ -# ] $param -# set param [ipx::get_user_parameters QPLL_LPF -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x37f : 0x137]]} \ -# ] $param -# set param [ipx::get_user_parameters RXCDR_CFG3_GEN2 -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x1a ]]} \ -# ] $param -# set param [ipx::get_user_parameters RXCDR_CFG3_GEN4 -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x24 ]]} \ -# ] $param -# set param [ipx::get_user_parameters TX_PI_BIASSET -of_objects $cc] -# set_property -dict [list \ -# value_tcl_expr {expr {$XCVR_TYPE == 9} ? 0 : 1} \ -# ] $param -# ipx::create_xgui_files [ipx::current_core] -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:25:46 2021... diff --git a/adi_library/xilinx/util_clkdiv/util_clkdiv_ip.log b/adi_library/xilinx/util_clkdiv/util_clkdiv_ip.log deleted file mode 100644 index c0b311e8..00000000 --- a/adi_library/xilinx/util_clkdiv/util_clkdiv_ip.log +++ /dev/null @@ -1,699 +0,0 @@ - -****** Vivado v2019.1.3 (64-bit) - **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 - **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source util_clkdiv_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_clkdiv -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_clkdiv'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_clkdiv [list \ -# "util_clkdiv_constr.xdc" \ -# "util_clkdiv_ooc.ttcl" \ -# "util_clkdiv.v" ] -# adi_ip_properties_lite util_clkdiv -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_clkdiv/util_clkdiv_ooc.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_ttcl util_clkdiv "util_clkdiv_ooc.ttcl" -# set_property processing_order LATE [ipx::get_files "util_clkdiv_constr.xdc" \ -# -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]] -# set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]] -# set_property value_validation_type list [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]] -# set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]] -# set_property value_validation_type list [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]] -# set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]] -# set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]] -# set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]] -# adi_add_bus clk_out master "xilinx.com:signal:clock_rtl:1.0" "xilinx.com:signal:clock:1.0" \ -# [list {"clk_out" "CLK"}] -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:24:37 2021... diff --git a/adi_library/xilinx/util_clkdiv/vivado.jou b/adi_library/xilinx/util_clkdiv/vivado.jou deleted file mode 100644 index bafe9784..00000000 --- a/adi_library/xilinx/util_clkdiv/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:24:30 2021 -# Process ID: 67236 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_clkdiv -# Command line: vivado -mode batch -source util_clkdiv_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_clkdiv/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_clkdiv/vivado.jou -#----------------------------------------------------------- -source util_clkdiv_ip.tcl diff --git a/adi_library/xilinx/util_clkdiv/vivado.log b/adi_library/xilinx/util_clkdiv/vivado.log deleted file mode 100644 index 351a1539..00000000 --- a/adi_library/xilinx/util_clkdiv/vivado.log +++ /dev/null @@ -1,704 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Dec 8 10:24:30 2021 -# Process ID: 67236 -# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_clkdiv -# Command line: vivado -mode batch -source util_clkdiv_ip.tcl -# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_clkdiv/vivado.log -# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_clkdiv/vivado.jou -#----------------------------------------------------------- -source util_clkdiv_ip.tcl -# source ../../scripts/adi_env.tcl -## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] -## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]] -## if [info exists ::env(ADI_HDL_DIR)] { -## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -## } -## if [info exists ::env(ADI_GHDL_DIR)] { -## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)] -## } -# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl -### variable auto_set_param_list -### variable auto_set_param_list_overwritable -### variable fpga_series_list -### variable fpga_family_list -### variable speed_grade_list -### variable dev_package_list -### variable xcvr_type_list -### variable fpga_voltage_list -### set auto_set_param_list { \ -### DEV_PACKAGE \ -### SPEED_GRADE \ -### FPGA_FAMILY \ -### FPGA_TECHNOLOGY } -### set auto_set_param_list_overwritable { \ -### FPGA_VOLTAGE \ -### XCVR_TYPE } -### set fpga_technology_list { \ -### { Unknown 0 } \ -### { 7series 1 } \ -### { ultrascale 2 } \ -### { ultrascale+ 3 }} -### set fpga_family_list { \ -### { Unknown 0 } \ -### { artix 1 } \ -### { kintex 2 } \ -### { virtex 3 } \ -### { zynq 4 }} -### set speed_grade_list { \ -### { Unknown 0 } \ -### { -1 10 } \ -### { -1L 11 } \ -### { -1H 12 } \ -### { -1HV 13 } \ -### { -1LV 14 } \ -### { -2 20 } \ -### { -2L 21 } \ -### { -2LV 22 } \ -### { -3 30 }} -### set dev_package_list { \ -### { Unknown 0 } \ -### { rf 1 } \ -### { fl 2 } \ -### { ff 3 } \ -### { fb 4 } \ -### { hc 5 } \ -### { fh 6 } \ -### { cs 7 } \ -### { cp 8 } \ -### { ft 9 } \ -### { fg 10 } \ -### { sb 11 } \ -### { rb 12 } \ -### { rs 13 } \ -### { cl 14 } \ -### { sf 15 } \ -### { ba 16 } \ -### { fa 17 } \ -### { fs 18 } \ -### { fi 19 }} -### set xcvr_type_list { \ -### { Unknown 0 } \ -### { GTPE2_NOT_SUPPORTED 1 } \ -### { GTXE2 2 } \ -### { GTHE2_NOT_SUPPORTED 3 } \ -### { GTZE2_NOT_SUPPORTED 4 } \ -### { GTHE3 5 } \ -### { GTYE3_NOT_SUPPORTED 6 } \ -### { GTRE4_NOT_SUPPORTED 7 } \ -### { GTHE4 8 } \ -### { GTYE4 9 } \ -### { GTME4_NOT_SUPPORTED 10}} -### set fpga_voltage_list {0 5000} ; -### proc adi_device_spec {cellpath param} { -### -### set list_pointer [string tolower $param] -### set list_pointer [append list_pointer "_list"] -### -### upvar 1 $list_pointer $list_pointer -### -### set ip [get_bd_cells $cellpath] -### set part [get_property PART [current_project]] -### -### switch -regexp -- $param { -### FPGA_TECHNOLOGY { -### switch -regexp -- $part { -### ^xc7 {set series_name 7series} -### ^xczu {set series_name ultrascale+} -### ^xc.u.p {set series_name ultrascale+} -### ^xc.u {set series_name ultrascale } -### default { -### puts "Undefined fpga technology for \"$part\"!" -### exit -1 -### } -### } -### return "$series_name" -### } -### FPGA_FAMILY { -### set fpga_family [get_property FAMILY $part] -### foreach i $fpga_family_list { -### regexp ^[lindex $i 0] $fpga_family matched -### } -### return "$matched" -### } -### SPEED_GRADE { -### set speed_grade [get_property SPEED $part] -### return "$speed_grade" -### } -### DEV_PACKAGE { -### set dev_package [get_property PACKAGE $part] -### foreach i $dev_package_list { -### regexp ^[lindex $i 0] $dev_package matched -### } -### return "$matched" -### } -### XCVR_TYPE { -### set matched "" -### set dev_transcivers "none" -### foreach x [list_property $part] { -### regexp ^GT..._TRANSCEIVERS $x dev_transcivers -### } -### foreach i $xcvr_type_list { -### regexp ^[lindex $i 0] $dev_transcivers matched -### } -### if { $matched eq "" } { -### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" -### } -### return "$matched" -### } -### FPGA_VOLTAGE { -### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] -### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) -### -### return "$fpga_voltage" -### } -### default { -### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" -### } -### } -### } -## if {![info exists REQUIRED_VIVADO_VERSION]} { -## set REQUIRED_VIVADO_VERSION "2019.1" -## } -## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { -## set IGNORE_VERSION_CHECK 1 -## } elseif {![info exists IGNORE_VERSION_CHECK]} { -## set IGNORE_VERSION_CHECK 0 -## } -## proc adi_ip_ttcl {ip_name ip_constr_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] -## set f [ipx::add_file $ip_constr_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_constr_files $proj_filegroup -## } -## proc adi_ip_sim_ttcl {ip_name ip_files} { -## -## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] -## set f [ipx::add_file $ip_files $proj_filegroup] -## set_property -dict [list \ -## type ttcl \ -## ] $f -## ipx::reorder_files -front $ip_files $proj_filegroup -## } -## proc adi_ip_bd {ip_name ip_bd_files} { -## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] -## if {$proj_filegroup == {}} { -## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] -## } -## -## foreach file $ip_bd_files { -## set f [ipx::add_file $file $proj_filegroup] -## set_property -dict [list \ -## type tclSource \ -## ] $f -## } -## } -## proc adi_ip_infer_streaming_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_ip_infer_mm_interfaces {ip_name} { -## -## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## } -## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { -## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { -## set_property ENABLEMENT_DEPENDENCY $dependency $port -## if {$driver_value != {}} { -## set_property DRIVER_VALUE $driver_value $port -## } -## } -## } -## proc adi_set_bus_dependency {bus prefix dependency} { -## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] -## adi_set_ports_dependency $prefix $dependency 0 -## } -## proc adi_add_port_map {bus phys logic} { -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## } -## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## foreach port_map $port_maps { -## adi_add_port_map $bus {*}$port_map -## } -## } -## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { -## for {set i 0} {$i < $num} {incr i} { -## set bus_name [format "%s%d" $bus_name_prefix $i] -## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] -## -## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus -## set_property "BUS_TYPE_VLNV" $bus_type $bus -## set_property "INTERFACE_MODE" $mode $bus -## -## if {$dependency ne ""} { -## set bus_dependency [string map [list "{i}" $i] $dependency] -## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus -## } -## -## foreach port_map $port_maps { -## lassign $port_map phys logic width width_dep -## set map [ipx::add_port_map $phys $bus] -## set_property "PHYSICAL_NAME" $phys $map -## set_property "LOGICAL_NAME" $logic $map -## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map -## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map -## if {$width_dep ne ""} { -## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map -## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map -## set width_dep_r "(($width_dep) * $i)" -## set width_dep_l "(($width_dep) * ($i + 1)-1)" -## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map -## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map -## } -## } -## } -## } -## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { -## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] -## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] -## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf -## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf -## set_property display_name $clock_inf_name $clock_inf -## set clock_map [ipx::add_port_map "CLK" $clock_inf] -## set_property physical_name $clock_signal_name $clock_map -## -## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] -## set_property value $bus_inf_name $assoc_busif -## -## if { $reset_signal_name != "" } { -## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] -## set_property value $reset_signal_name $assoc_reset -## -## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] -## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] -## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf -## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf -## set_property display_name $reset_inf_name $reset_inf -## set_property interface_mode $reset_signal_mode $reset_inf -## set reset_map [ipx::add_port_map "RST" $reset_inf] -## set_property physical_name $reset_signal_name $reset_map -## -## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] -## if {[string match {*[Nn]} $reset_signal_name] == 1} { -## set_property value "ACTIVE_LOW" $reset_polarity -## } else { -## set_property value "ACTIVE_HIGH" $reset_polarity -## } -## } -## } -## proc adi_ip_add_core_dependencies {vlnvs} { -## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { -## foreach vlnv $vlnvs { -## ipx::add_subcore $vlnv $file_group -## } -## } -## } -## proc adi_ip_create {ip_name} { -## -## global ad_hdl_dir -## global ad_ghdl_dir -## global REQUIRED_VIVADO_VERSION -## global IGNORE_VERSION_CHECK -## -## set VIVADO_VERSION [version -short] -## if {$IGNORE_VERSION_CHECK} { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "CRITICAL WARNING: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## } -## } else { -## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { -## puts -nonewline "ERROR: vivado version mismatch; " -## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " -## puts -nonewline "got $VIVADO_VERSION.\n" -## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" -## exit 2 -## } -## } -## -## create_project $ip_name . -force -## -## ## Load custom message severity definitions -## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl -## -## set lib_dirs $ad_hdl_dir/library -## if {$ad_hdl_dir ne $ad_ghdl_dir} { -## lappend lib_dirs $ad_ghdl_dir/library -## } -## -## set_property ip_repo_paths $lib_dirs [current_fileset] -## update_ip_catalog -## } -## proc adi_ip_files {ip_name ip_files} { -## set proj_fileset [get_filesets sources_1] -## foreach m_file $ip_files { -## if {[file extension $m_file] eq ".xdc"} { -## add_files -norecurse -fileset constrs_1 $m_file -## } else { -## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file -## } -## } -## set_property "top" "$ip_name" $proj_fileset -## } -## proc adi_ip_properties_lite {ip_name} { -## -## global ad_hdl_dir -## -## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices -## -## set_property name $ip_name [ipx::current_core] -## -## set_property vendor_display_name {Analog Devices} [ipx::current_core] -## set_property company_url {http://www.analog.com} [ipx::current_core] -## -## set i_families "" -## foreach i_part [get_parts] { -## lappend i_families [get_property FAMILY $i_part] -## } -## set i_families [lsort -unique $i_families] -## set s_families [get_property supported_families [ipx::current_core]] -## foreach i_family $i_families { -## set s_families "$s_families $i_family Production" -## set s_families "$s_families $i_family Beta" -## } -## set_property supported_families $s_families [ipx::current_core] -## -## ipx::save_core [ipx::current_core] -## -## ipx::remove_all_bus_interface [ipx::current_core] -## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] -## foreach map $memory_maps { -## ipx::remove_memory_map [lindex $map 2] [ipx::current_core] -## } -## -## ipx::update_checksums [ipx::current_core] -## ipx::save_core [ipx::current_core] -## } -## proc adi_ip_properties {ip_name} { -## -## adi_ip_properties_lite $ip_name -## -## ipx::infer_bus_interface {\ -## s_axi_awvalid \ -## s_axi_awaddr \ -## s_axi_awprot \ -## s_axi_awready \ -## s_axi_wvalid \ -## s_axi_wdata \ -## s_axi_wstrb \ -## s_axi_wready \ -## s_axi_bvalid \ -## s_axi_bresp \ -## -## s_axi_bready \ -## s_axi_arvalid \ -## s_axi_araddr \ -## s_axi_arprot \ -## s_axi_arready \ -## s_axi_rvalid \ -## s_axi_rdata \ -## s_axi_rresp \ -## s_axi_rready} \ -## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] -## -## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] -## -## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] -## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] -## -## if {$raddr_width != $waddr_width} { -## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] -## set range 65536 -## } else { -## if {$raddr_width >= 16} { -## set range 65536 -## } else { -## set range [expr 1 << $raddr_width] -## } -## } -## -## ipx::add_memory_map {s_axi} [ipx::current_core] -## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] -## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] -## set_property range $range [ipx::get_address_blocks axi_lite \ -## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] -## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] -## ipx::save_core -## } -## proc adi_init_bd_tcl {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## if { [file exists bd] } { -## file delete -force bd -## } -## file mkdir bd -## -## set bd_tcl [open "bd/bd.tcl" w] -## -## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" -## puts $bd_tcl "proc init {cellpath otherInfo} {" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl "" -## set auto_set_param "" -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_param " $i \\\n" -## } -## } -## if { $auto_set_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" -## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param -## puts $bd_tcl $auto_set_param -## } -## -## set auto_set_overwritable_param "" -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { -## append auto_set_overwritable_param " $i \\\n" -## } -## } -## if { $auto_set_overwritable_param ne "" } { -## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" -## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param -## puts $bd_tcl $auto_set_overwritable_param -## } -## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" -## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" -## puts $bd_tcl "" -## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" -## puts $bd_tcl " set ip_param_list \[list_property \$ip\]" -## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" -## puts $bd_tcl "" -## puts $bd_tcl " set parent_dir \"../\"" -## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" -## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " if { \[file exists \$linkname\] } {" -## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" -## puts $bd_tcl " break" -## puts $bd_tcl " }" -## puts $bd_tcl " append parent_dir \"../\"" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "" -## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" -## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" -## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" -## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" -## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" -## puts $bd_tcl " }" -## puts $bd_tcl " }" -## puts $bd_tcl "}" -## puts $bd_tcl "" -## close $bd_tcl -## -## set proj_fileset [get_filesets sources_1] -## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" -## -## set local_mk [open "temporary_case_dependencies.mk" w] -## seek $local_mk 0 start -## puts $local_mk "CLEAN_TARGET += bd" -## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" -## close $local_mk -## } -## proc adi_add_auto_fpga_spec_params {} { -## -## global auto_set_param_list -## global auto_set_param_list_overwritable -## set cc [ipx::current_core] -## -## foreach i $auto_set_param_list { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## foreach i $auto_set_param_list_overwritable { -## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { -## adi_add_device_spec_param $i -## } -## } -## } -## proc adi_add_device_spec_param {ip_param} { -## -## set cc [ipx::current_core] -## -## set list_pointer [string tolower $ip_param] -## set list_pointer [append list_pointer "_list"] -## -## global $list_pointer -## -## # set j 1D list from the original list -## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} -## -## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) -## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { -## set_property -dict [list \ -## "value_validation_type" "range_long" \ -## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ -## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } else { -## set_property -dict [list \ -## "value_validation_type" "pairs" \ -## "value_validation_pairs" $j ] \ -## [ipx::get_user_parameters $ip_param -of_objects $cc] -## } -## -## # FPGA info grup -## set info_group_name "FPGA info" -## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] -## if { [string trim $info_group] eq "" } { -## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] -## set info_group [ipgui::add_group -name $info_group_name -component $cc \ -## -parent $page0 -display_name $info_group_name] -## } -## -## set p [ipgui::get_guiparamspec -name $ip_param -component $cc] -## set_property -dict [list "widget" "comboBox" ] $p -## ipgui::move_param -component $cc -order 0 $p -parent $info_group -## } -## proc adi_if_define {name} { -## -## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 -## ipx::create_bus_definition analog.com interface $name 1.0 -## -## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] -## set_property xml_file_name ${name}.xml [ipx::current_busdef] -## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] -## -## ipx::save_abstraction_definition [ipx::current_busabs] -## ipx::save_bus_definition [ipx::current_busdef] -## } -## proc adi_if_ports {dir width name {type none}} { -## -## ipx::add_bus_abstraction_port $name [ipx::current_busabs] -## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] -## set_property master_presence required $m_intf -## set_property slave_presence required $m_intf -## set_property master_width $width $m_intf -## set_property slave_width $width $m_intf -## -## set m_dir "in" -## set s_dir "out" -## if {$dir eq "output"} { -## set m_dir "out" -## set s_dir "in" -## } -## -## set_property master_direction $m_dir $m_intf -## set_property slave_direction $s_dir $m_intf -## -## if {$type ne "none"} { -## set_property is_${type} true $m_intf -## } -## -## ipx::save_bus_definition [ipx::current_busdef] -## ipx::save_abstraction_definition [ipx::current_busabs] -## } -## proc adi_if_infer_bus {if_name mode name maps} { -## -## ipx::add_bus_interface $name [ipx::current_core] -## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] -## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if -## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if -## set_property interface_mode $mode $m_bus_if -## -## foreach map $maps { -## set m_maps [regexp -all -inline {\S+} $map] -## lassign $m_maps p_name p_map -## ipx::add_port_map $p_name $m_bus_if -## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] -## } -## } -# adi_ip_create util_clkdiv -CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3. -## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING -## set_msg_config -id {BD 41-1343} -new_severity WARNING -## set_msg_config -id {BD 41-1306} -new_severity WARNING -## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR -## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO -## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO -## set_msg_config -id {IP_Flow 19-459} -new_severity INFO -## set_msg_config -id {Synth 8-3331} -new_severity INFO -## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO -## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING -## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'. -INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_clkdiv'.) -WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path. -If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'. -# adi_ip_files util_clkdiv [list \ -# "util_clkdiv_constr.xdc" \ -# "util_clkdiv_ooc.ttcl" \ -# "util_clkdiv.v" ] -# adi_ip_properties_lite util_clkdiv -WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_clkdiv/util_clkdiv_ooc.ttcl' ignored by IP packager. -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). -WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing. -INFO: [IP_Flow 19-2181] Payment Required is not set for this core. -INFO: [IP_Flow 19-2187] The Product Guide file is missing. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files. -# adi_ip_ttcl util_clkdiv "util_clkdiv_ooc.ttcl" -# set_property processing_order LATE [ipx::get_files "util_clkdiv_constr.xdc" \ -# -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]] -# set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]] -# set_property value_validation_type list [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]] -# set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]] -# set_property value_validation_type list [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]] -# set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]] -# set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]] -# set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]] -# adi_add_bus clk_out master "xilinx.com:signal:clock_rtl:1.0" "xilinx.com:signal:clock:1.0" \ -# [list {"clk_out" "CLK"}] -# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] -INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument). -# ipx::save_core [ipx::current_core] -INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:24:37 2021...